參數(shù)資料
型號(hào)： DSM2190F4V
廠商： 意法半導(dǎo)體
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-bit fixed point DSP with Flash
中文描述： 具有閃存的 16 位定點(diǎn) DSP
文件頁(yè)數(shù)： 26/61頁(yè)
文件大?。?/td> 530K
代理商： DSM2190F4V
DSM2190F4
26/61
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. See application
note AN1171for details on how to specify logic us-
ing PSDsoft Express.
As shown in Figure 15, the CPLD has the following
blocks:
I
16 Input Macrocells (IMC)
I
16 Output Macrocells (OMC)
I
Macrocell Allocator
I
Product Term Allocator
I
AND Array capable of generating up to 130
product terms
I
Two I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the device internal data
bus and can be directly accessed by the DSP. This
enables the DSP software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macro cell architectures.
Figure 15. Macrocell and I/O Port
Output Macrocell (OMC).
Eight of the Output
Macrocells (OMC) are connected to Port B pins
and are named as McellAB0-McellAB7. The other
eight Macrocells are connected to Ports B or C
pins and are named as McellBC0-McellBC7.
OMCs may be used for internal feedback only
(buried registers), or their outputs may be routed
to external Port pins.
The Output Macrocell (OMC) architecture is
shown in Figure 17. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
I/O PORTS
CPLD Macrocells
Input Macrocells
LATCHED
ADDRESS OUT
MUX
M
M
M
D
D
Q
Q
Q
G
D
Q D
WR
WR
PDR
DATA
PALLOCATOR
DIR
SELECT
INPUT
Pfrom other
MacrocellS
POLARITY
PROUP TO 10
CLOCK
PR
DI LD
D/T
CK
CL
Q
SELECT
PT CLEAR
PT
GLOBAL
PT Output Enable (OE)
Macrocell Feedback
I/O Port Input
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET
MCU DATA IN
/REG
SELECT
Mato
IAlloc.
OCPLD
TO OTHER I/O PORTS
P
P
DSP ADDRESS / DATA BUS
MOut to
MCU
CDATA
A
CPLD OUTPUT
I/O Pin
AI04902B
相關(guān)PDF資料
PDF描述
DSM2190F4V-15K6 16-bit fixed point DSP with Flash
DSM2190F4V-15T6 16-bit fixed point DSP with Flash
DSM3MA GENERAL-USE RECTIFIER DIODE
DSP-A1092 NATURAL SOUND AV AMPLIFIRE
DSP101 DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
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DSM2190F4V-15K6 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 3.3V 16M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
DSM2190F4V-15T6 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 3.3V 16M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
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