參數(shù)資料
型號： DSP56301PW100
廠商： Freescale Semiconductor
文件頁數(shù)： 30/124頁
文件大?。?/td> 0K
描述： IC DSP 24BIT FIXED-POINT 208LQFP
標(biāo)準(zhǔn)包裝： 36
系列： DSP563xx
類型： 定點
接口： 主機接口，SSI，SCI
時鐘速率： 100MHz
非易失內(nèi)存： ROM（9 kB）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP
供應(yīng)商設(shè)備封裝： 208-LQFP
包裝： 托盤
Interrupt and Mode Control
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
1-9
1.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After
RESET
is deasserted, these inputs are hardware interrupt request lines.
Table 1-9.
Interrupt and Mode Control
Signal Name
Type
State During
Reset
Signal Description
MODA
IRQA
Input
Mode Select A
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
IRQA during normal instruction processing. MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes, latched into the OMR
when the RESET signal is deasserted.
External Interrupt Request A
Internally synchronized to CLKOUT. If IRQA is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQA to exit the Wait state. If the processor is in the
Stop stand-by state and IRQA is asserted, the processor exits the Stop state.
These inputs are 5 V tolerant.
MODB
IRQB
Input
Mode Select B
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
IRQB during normal instruction processing. MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes, latched into the OMR
when the RESET signal is deasserted.
External Interrupt Request B
Internally synchronized to CLKOUT. If IRQB is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQB to exit the Wait state. If the processor is in the
Stop stand-by state and IRQC is asserted, the processor will exit the Stop
state.
These inputs are 5 V tolerant.
MODC
IRQC
Input
Mode Select C
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
IRQC during normal instruction processing. MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes, latched into the OMR
when the RESET signal is deasserted.
External Interrupt Request C
Internally synchronized to CLKOUT. If IRQC is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQC to exit the Wait state. If the processor is in the
Stop stand-by state and IRQC is asserted, the processor exits the Stop state.
These inputs are 5 V tolerant.
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