HDBDR High from Read Data Strobe Deas" />
參數(shù)資料
型號(hào)： DSP56301PW80
廠商： Freescale Semiconductor
文件頁數(shù)： 83/124頁
文件大小： 0K
描述： IC DSP 24BIT 80MHZ 208-LQFP
標(biāo)準(zhǔn)包裝： 36
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 80MHz
非易失內(nèi)存： ROM（9 kB）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP
供應(yīng)商設(shè)備封裝： 208-LQFP
包裝： 托盤
AC Electrical Characteristics
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-35
345
HDBDR High from Read Data Strobe Deassertion3
—
22.2
—
19.6
ns
346
HRST Assertion to Host Port Pins High Impedance2
—
22.2
—
19.6
ns
Notes:
1.
The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
2.
HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST
are shown as active-high and HTA is shown as active low.
3.
The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
4.
The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
5.
HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if
programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications.
6.
HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent
with the DC specifications.
7.
“LT” is the value of the latency timer register (CLAT) as programmed by the user during self configuration.
LT
≥ 1.
8.
Values are valid for VCC = 3.3 ± 0.3V
Table 2-19.
Universal Bus Mode, Synchronous Port A Type Host Timing
No.
Characteristic
Expression
80 MHz
100 MHz
Unit
Min
Max
Min
Max
300
Access Cycle Time
3
× TC
37.5
—
30.0
—
ns
301
HA[10–0], HAEN Setup to Data Strobe Assertion1
5.8
—
4.6
—
ns
302
HA[10–0], HAEN Valid Hold from Data Strobe Deassertion1
0.0
—
0.0
—
ns
305
Data Strobe Deasserted Width1
4.1
—
3.3
—
ns
307
HBS Asserted Pulse Width
2.5
—
2.0
—
ns
308
HBS Assertion to Data Strobe Assertion1
80 MHz: TC 4.9
100 MHz: TC 4.0
—7.6
—6.0
ns
309
HBS Assertion to Data Strobe Deassertion1
80 MHz: 2.5
× TC + 2.9
100 MHz: 2.5
× TC + 2.3
34.1
—
27.3
—
ns
310
HBS Deassertion to Data Strobe Deassertion1
80 MHz: 1.5
× TC + 3.3
100 MHz: 1.5
× TC + 2.6
22.1
—
17.6
—
ns
312
Data Out Active from Read Data Strobe Assertion3
1.7
—
1.3
—
ns
313
Data Out Valid from Read Data Strobe Assertion
(No Wait States Inserted—HTA Asserted)3
—
18.9
—
16.9
ns
314
Data Out Valid Hold from Read Data Strobe Deassertion3
1.7
—
1.3
—
ns
315
Data Out High Impedance from Read Data Strobe Deassertion3
—
12.0
—
9.6
ns
316
Data In Valid Setup to Write Data Strobe Deassertion4
8.3
—
6.6
—
ns
317
Data In Valid Hold from Write Data Strobe Deassertion4
0.0
—
0.0
—
ns
324
HTA Assertion to Data Strobe Deassertion1,2
0.0
—
0.0
—
ns
325
HTA High Impedance from Data Strobe Deassertion1,2
—
15.3
—
12.2
ns
326
HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)
(LT + 1)
× TC 6.07
6.5
—
4.0
—
ns
327
Data Strobe Deasserted Hold from HIRQ Deassertion
(HIRH = 0)1
0.0
—
0.0
—
ns
328
HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)1
1.5
× TC
18.8
—
15.0
—
ns
329
HIRQ Deassertion from Data Strobe Assertion
(HIRH = 1, HIRD = 1)1
80 MHz: 2.5
× TC + 24.7
100 MHz: 2.5
× TC + 21.5
—
55.9
—
46.5
ns
Table 2-18.
Universal Bus Mode Timing Parameters (Continued)
No.
Characteristic
Expression
80 MHz
100 MHz
Unit
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
VE-26Z-CW-S CONVERTER MOD DC/DC 2V 40W
MIC281-0BM6 TR IC SUPERVISOR THERMAL SOT23-6
VJ1206A821JBBAT4X CAP CER 820PF 100V 5% NP0 1206
VI-21D-CW-F4 CONVERTER MOD DC/DC 85V 100W
EBC05DRES-S13 CONN EDGECARD 10POS .100 EXTEND
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56301UMAD 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56301 Users Manual Addendum
DSP56301VF100 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 100Mhz/100MMACS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56301VF80 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC MAP DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56301VF80B1 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC DSP56301VF80B1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56301VL100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Digital Signal Processor
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*