參數(shù)資料
型號: DSP56600
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
中文描述: 維特比解碼器實現(xiàn)上使用DSP的家庭教學(xué)的VSL
文件頁數(shù): 105/108頁
文件大?。?/td> 726K
代理商: DSP56600
24-Bit Algorithm Program Listing
Viterbi Decoder Implementation
For More Information On This Product,
Go to: www.freescale.com
C-13
;**********************MEMORY ORGANIZATION****************************
;
MOST OF THE MEMORY LOCATION IS IMPORTANT--THE FIRST TWO
;
LABELS OF THE X AND Y DATA MEMORY ARE PAIRED AND MUST
;
BE CO LOCATED (AT THE SAME ADDRESSES). IN ADDITION, STATE1
;
AND STATE2 MUST BE LOCATED ON A 0 MOD 2*NUMSTATES BOUNDARY,
;
X and Y memory for input data must be paired --GOOD LUCK.....
;*********************************************************************
;
org
x:$0
STATE1
DC
$0ff,$0,$0,$0,$0,$0,$0,$0,0,0,0,0,0,0,0,0
DC
$0,$0,$0,$0,$0,$0,$0,$0,0,0,0,0,0,0,0,0
STATE2
DC
$0ff,$0,$0,$0,$0,$0,$0,$0,0,0,0,0,0,0,0,0
DC
$0,$0,$0,$0,$0,$0,$0,$0,0,0,0,0,0,0,0,0
BRX
DSM
NUMSTATES/2
;
PATHOUT DS
NUMSTATES*(NUMINPUTS/8+1)
INDATA ;THIS DATA ENCODES
$1234,$5678,$9abc,$4973,$7925,$3491,$ad43,$ff21,$7ebb,$0100,$20
DC
$a00000,$a00000,$a00000,$600000,$600000,$a00000,$a00000,$600000
DC
$600000,$600000,$600000,$600000,$600000,$a00000,$a00000,$600000
DC
$a00000,$600000,$a00000,$600000,$a00000,$600000,$a00000,$600000
DC
$a00000,$a00000,$600000,$600000,$600000,$a00000,$a00000,$a00000
DC
$a00000,$a00000,$a00000,$a00000,$a00000,$a00000,$a00000,$a00000
DC
$a00000,$600000,$600000,$a00000,$a00000,$a00000,$a00000,$a00000
DC
$a00000,$a00000,$a00000,$a00000,$a00000,$600000,$600000,$a00000
DC
$600000,$a00000,$600000,$a00000,$600000,$600000,$600000,$600000
DC
$a00000,$a00000,$600000,$600000,$a00000,$a00000,$a00000,$600000
DC
$a00000,$600000,$a00000,$600000,$600000,$a00000,$600000,$a00000
DC
$a00000,$a00000,$600000,$a00000,$a00000,$a00000,$a00000,$600000
DC
$600000,$600000,$600000,$a00000,$600000,$600000,$600000,$600000
DC
$600000,$600000,$a00000,$a00000,$a00000,$a00000,$600000,$600000
DC
$a00000,$a00000,$600000,$a00000,$a00000,$a00000,$a00000,$a00000
DC
$a00000,$600000,$600000,$a00000,$a00000,$a00000,$a00000,$a00000
DC
$600000,$a00000,$600000,$a00000,$600000,$600000,$a00000,$a00000
DC
$600000,$600000,$600000,$a00000,$a00000,$600000,$a00000,$600000
DC
$600000,$600000,$a00000,$a00000,$a00000,$600000,$a00000,$a00000
DC
$a00000,$a00000,$600000,$600000,$600000,$a00000,$a00000,$600000
DC
$600000,$a00000,$600000,$a00000,$600000,$a00000,$a00000,$a00000
DC
$a00000,$a00000,$600000,$600000,$a00000,$600000,$a00000,$600000
;
Example C-1
24-bit Algorithm Program Listing (Continued)
F
Freescale Semiconductor, Inc.
n
.
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