參數(shù)資料
型號: DSP56600
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
中文描述: 維特比解碼器實(shí)現(xiàn)上使用DSP的家庭教學(xué)的VSL
文件頁數(shù): 19/108頁
文件大?。?/td> 726K
代理商: DSP56600
The Viterbi Algorithm
Viterbi Decoder
Viterbi Decoder Implementation
For More Information On This Product,
Go to: www.freescale.com
2-5
Figure 2-2
shows the entire tree used by the decoder to track the first five input pairs. The state of
the recreated encoder appears in the box. Along each arrow (a state transition) appears a
number pair showing the corresponding encoder output bit pair for that state transition
(the output produced immediately before the state changes). This figure is ordered so
that transitions corresponding to an input 0 are always the upper path and transitions
corresponding to an input 1 are always the lower path. To determine the encoder output
for a given transition, load the encoder with the state and use a 0 or 1 for the input bit,
according to the transition chosen. The encoder polynomials then determine the encoder
output, as shown in
Figure 2-1
.
shows a prototype for one state of the state tree for this decoder.
Figure 2-3
Figure 2-2
Single State of Prototype Encoder Tree Diagram
SaeTranston
Encoder Output
/
Branch Metric
Path Metric State
F
Freescale Semiconductor, Inc.
n
.
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