參數(shù)資料
型號: DSP56600
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
中文描述: 維特比解碼器實現(xiàn)上使用DSP的家庭教學(xué)的VSL
文件頁數(shù): 36/108頁
文件大?。?/td> 726K
代理商: DSP56600
3-8
Viterbi Decoder Implementation
For More Information On This Product,
Go to: www.freescale.com
Expanding the Viterbi Algorithm
Creating the Branch Metrics
Table 3-1
Recreated Encoder Outputs
The code needed to implement the values in this table appears in
Example 3-2
.
State
Input
Bit
Encoder
Output
Map Encoder Output to
Branch Metric
Branch Metric for Example
Decoder 10 Input
00000
1
11
B
0
+B
1
16 + (-16) = 0
00001
1
01
-B
0
+B
1
(-16) + (-16) = -32
00010
1
10
B
0
-B
1
32
00011
1
00
-B
0
-B
1
0
00100
1
00
-B
0
-B
1
0
00101
1
10
B
0
-B
1
32
00110
1
01
-B
0
+B
1
-32
00111
1
11
B
0
+B
1
0
01000
1
10
B
0
-B
1
32
01001
1
00
-B
0
-B
1
0
01010
1
11
B
0
+B
1
0
01011
1
01
-B
0
+B
1
-32
01100
1
01
-B
0
+B
1
-32
01101
1
11
B
0
+B
1
0
01110
1
00
-B
0
-B
1
0
01111
1
10
B
0
-B
1
32
F
Freescale Semiconductor, Inc.
n
.
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