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參數(shù)資料
| 型號(hào)： | DSPB56362AG120 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 16/152頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT AUD 120MHZ 144-LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | DSP56K/Symphony |
| 類型： | 音頻處理器 |
| 接口： | 主機(jī)接口，I²C，SAI，SPI |
| 時(shí)鐘速率： | 120MHz |
| 非易失內(nèi)存： | ROM（126 kB） |
| 芯片上RAM： | 42kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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PLL Performance Issues
DSP56362 Technical Data, Rev. 4
5-4
Freescale Semiconductor
Disable unused peripherals.
Disable unused pin activity (e.g., CLKOUT, XTAL).
One way to evaluate power consumption is to use a current per MIPS measurement methodology to
minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP).
A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific
test current measurements, and the following equation to derive the current per MIPS value.
where :
ItypF2 = current at F2
ItypF1 = current at F1
F2
= high frequency (any specified operating frequency)
F1
= low frequency (any specified operating frequency lower than F2)
NOTE
F1 should be significantly less than F2. For example, F2 could be 66 MHz
and F1 could be 33 MHz. The degree of difference between F1 and F2
determines the amount of precision with which the current rating can be
determined for an application.
5.4
PLL Performance Issues
The following explanations should be considered as general observations on expected PLL behavior.
There is no testing that verifies these exact numbers. These observations were measured on a limited
number of parts and were not verified over the entire temperature and voltage ranges.
5.4.1
Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and
CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature, and voltage
ranges. As defined in Figure 3-1, for input frequencies greater than 15 MHz and the MF
≤ 4, this skew is
greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for
MF < 10 and input frequencies greater than 10 MHz, this skew is between
1.4 ns and +3.2 ns.
5.4.2
Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL
and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load
on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater
than 15 MHz and MF
≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However,
for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than
±2 ns.
1MIPS
1MHz
I
(
typF2
ItypF1)
F2 F1
–
()
×
–
==
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSPB56364AF100 | IC DSP 24BIT AUD 100MHZ 100-LQFP |
| DSPB56366AG120 | IC DSP 24BIT AUD 120MHZ 144-LQFP |
| DSPB56367AG150 | IC DSP 24BIT 150MHZ 144-LQFP |
| DSPB56371AF180 | IC DSP 24BIT 180MHZ 80-LQFP |
| DSPB56374AEC | IC DSP 24BIT 150MHZ 52-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSPB56362AG120 | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSPB56362PV100 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk |
| DSPB56362PV120 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk |
| DSPB56364AF100 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC DSP56364 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSPB56364FU100 | 制造商:Rochester Electronics LLC 功能描述:24 BIT AUDIO DSP - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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