參數(shù)資料
型號： DSPB56362AG120
廠商： Freescale Semiconductor
文件頁數(shù)： 18/152頁
文件大?。?/td> 0K
描述： IC DSP 24BIT AUD 120MHZ 144-LQFP
標(biāo)準(zhǔn)包裝： 60
系列： DSP56K/Symphony
類型： 音頻處理器
接口： 主機接口，I²C，SAI，SPI
時鐘速率： 120MHz
非易失內(nèi)存： ROM（126 kB）
芯片上RAM： 42kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
Host Port Considerations
DSP56362 Technical Data, Rev. 4
5-6
Freescale Semiconductor
significance, the host could read the wrong combination. Therefore, read the bits twice and
check for consensus.
Overwriting the Host Vector
—The host interface programmer should change the host vector
(HV) register only when the host command (HC) bit is clear. This ensures that the DSP interrupt
control logic will receive a stable vector.
Cancelling a Pending Host Command Exception
—The host processor may elect to clear the HC
bit to cancel the host command exception request at any time before it is recognized by the DSP.
Because the host does not know exactly when the exception will be recognized (due to exception
processing synchronization and pipeline delays), the DSP may execute the host command
exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the
same time that the HC bit is cleared.
Variance in the Host Interface Timing
—The host interface (HDI) may vary (e.g. due to the PLL
lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make
sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then
polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together
with the INIT and then polling INIT, ISR, and the HOREQ pin).
5.5.2
DSP Programming Considerations
Synchronization of Status Bits from Host to DSP
—DMA, HF1, HF0, HCP, HTDE, and HRDF
status bits are set or cleared by the host processor side of the interface. These bits are individually
synchronized to the DSP clock. (Refer to the user’s manual for descriptions of these status bits.)
Reading HF0 and HF1 as an Encoded Pair
—Care must be exercised when reading status bits
HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have
significance). A very small probability exists that the DSP will read the status bits synchronized
during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSPB56362AG120 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
DSPB56362PV100 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk
DSPB56362PV120 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk
DSPB56364AF100 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSP56364 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPB56364FU100 制造商:Rochester Electronics LLC 功能描述:24 BIT AUDIO DSP - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述:
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