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參數(shù)資料
| 型號： | DSPB56362AG120 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 2/152頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT AUD 120MHZ 144-LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | DSP56K/Symphony |
| 類型： | 音頻處理器 |
| 接口： | 主機(jī)接口，I²C，SAI，SPI |
| 時鐘速率： | 120MHz |
| 非易失內(nèi)存： | ROM（126 kB） |
| 芯片上RAM： | 42kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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Ground
DSP56362 Technical Data, Rev. 4
2-4
Freescale Semiconductor
2.3
Ground
2.4
Clock and PLL
Table 2-3 Grounds
Ground Name
Description
GNDP
PLL Ground—GNDP is a ground dedicated for PLL use. The connection should be provided with an
extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor
located as close as possible to the chip package. There is one GNDP connection.
GNDP1
PLL Ground 1—GNDP1 is a ground dedicated for PLL use. The connection should be provided with an
extremely low-impedance path to ground. There is one GNDP1 connection.
GNDQ (4)
Quiet Ground—GNDQ is an isolated ground for the internal processing logic. This connection must be
tied externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There are four GNDQ connections.
GNDA (4)
Address Bus Ground—GNDA is an isolated ground for sections of the address bus I/O drivers. This
connection must be tied externally to all other chip ground connections. The user must provide adequate
external decoupling capacitors. There are four GNDA connections.
GNDD (4)
Data Bus Ground—GNDD is an isolated ground for sections of the data bus I/O drivers. This connection
must be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are four GNDD connections.
GNDC (2)
Bus Control Ground—GNDC is an isolated ground for the bus control I/O drivers. This connection must
be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are two GNDC connections.
GNDH
Host Ground—GNDH is an isolated ground for the HDI08 I/O drivers. This connection must be tied
externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There is one GNDH connection.
GNDS (2)
SHI, ESAI, DAX, and Timer Ground—GNDS is an isolated ground for the SHI, ESAI, DAX, and Timer
I/O drivers. This connection must be tied externally to all other chip ground connections. The user must
provide adequate external decoupling capacitors. There are two GNDS connections.
Table 2-4 Clock and PLL Signals
Signal Name
Type
State during Reset
Signal Description
EXTAL
Input
External Clock Input—An external clock source must be connected to EXTAL
in order to supply the clock to the internal clock generator and PLL.
This input cannot tolerate 5V.
CLKOUT
Output
Chip-Driven
Clock Output—CLKOUT provides an output clock synchronized to the internal
core clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
CLKOUT is not functional at frequencies of 100 MHz and above.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSPB56362AG120 | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSPB56362PV100 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk |
| DSPB56362PV120 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk |
| DSPB56364AF100 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSP56364 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSPB56364FU100 | 制造商:Rochester Electronics LLC 功能描述:24 BIT AUDIO DSP - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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