參數(shù)資料
型號: DSPB56362AG120
廠商: Freescale Semiconductor
文件頁數(shù): 78/152頁
文件大小: 0K
描述: IC DSP 24BIT AUD 120MHZ 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機(jī)接口,I²C,SAI,SPI
時鐘速率: 120MHz
非易失內(nèi)存: ROM(126 kB)
芯片上RAM: 42kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
EXTERNAL CLOCK OPERATION
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
3-5
3.7
EXTERNAL CLOCK OPERATION
The DSP56362 system clock is an externally supplied square wave voltage source connected to EXTAL
Figure 3-1 External Clock Timing
Table 3-5 Clock Operation 100 and 120 MHz Values
No.
Characteristics
Symbol
100 MHz
120 MHz
Min
Max
Min
Max
1
Frequency of EXTAL (EXTAL Pin Frequency)
The rise and fall time of this external clock should be 3 ns
maximum.
Ef
0
100.0
0
120.0
2
EXTAL input high1, 2
With PLL disabled (46.7%–53.3% duty cycle)3
With PLL enabled (42.5%–57.5% duty cycle)3
ETH
4.67 ns
4.25 ns
157.0
s
0.00 ns
157.0
s
3
EXTAL input low1, 2
With PLL disabled (46.7%–53.3% duty cycle)3
With PLL enabled (42.5%–57.5% duty cycle)3
ETL
4.67 ns
4.25 ns
157.0
s
4.67 ns
4.25 ns
1570.00
4
EXTAL cycle time2
With PLL disabled
With PLL enabled
ETC
10.00 ns
273.1
s
8.33 ns
273.1
s
5
CLKOUT change from EXTAL fall with PLL disabled
4.3 ns
11.0 ns
EXTAL
VILC
VIHC
Midpoint
Note: The midpoint is 0.5 (VIHC + VILC).
ETH
ETL
ETC
CLKOUT With
PLL Disabled
CLKOUT With
PLL Enabled
7
5
7
6b
5
3
4
2
AA0459
6a
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