271
SAM4CP [DATASHEET]
43051E–ATPL–08/14
RSTC_CPMR.CPEREN: Writing a 0 to CPEREN resets all the embedded peripherals associated to coprocessor
whereas the processor peripherals are not reset.
RSTC_CR.EXTRST: Writing a 1 to EXTRST asserts low the NRST pin during a time defined by the field
RSTC_MR.ERSTL.
The software reset is entered if at least one of these bits is set by the software. All these commands can be performed
independently or simultaneously. The software reset lasts 3 Slow Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock
(MCK). They are released when the software reset has ended, i.e.; synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the configuration of the field RSTC_MR.ERSTL. However,
the resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in field RSTC_SR.RSTTYP. Other
Software Resets are not reported in RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the
RSTC_SR. SRCMP is cleared at the end of the software reset. No other software reset can be performed while the
SRCMP bit is set, and writing any value in the RSTC_CR has no effect.
Figure 15-5.
Software Reset
15.4.3.5 User Reset
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1.
The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor and Coprocessor Reset and
the Peripheral Resets are asserted.
The User Reset ends when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup.
The processor clock is re-enabled as soon as NRST is confirmed high.
SLCK
periph_nreset
if PERRST=1
proc_nreset
if PROCRST=1
Write RSTC_CR
NRST
(nrst_out)
if EXTRST=1
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 2 cycles
Any
Freq.
RSTTYP
Any
XXX
0x3 = Software Reset
Resynch.
1 cycle
SRCMP in RSTC_SR