708
SAM4CP [DATASHEET]
43051E–ATPL–08/14
34.8.6 TWI Status Register
Name:
TWI_SR
Address:
0x40018020 (0), 0x4001C020 (1)
Access:
Read-only
TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding register and internal shifter are empty and STOP condition has been sent.
TXCOMP behavior in Master mode
can be seen in
Figure 34-8 on page 680
and in
Figure 34-10 on page 681
.
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode
can be seen in
Figure 34-29 on page 697
,
Figure 34-30 on page 698
,
Figure 34-31 on page
698
and
Figure 34-32 on page 699
.
RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode
can be seen in
Figure 34-10 on page 681
.
RXRDY behavior in Slave mode
can be seen in
Figure 34-27 on page 696
,
Figure 34-30 on page 698
,
Figure 34-31 on page 698
and
Figure 34-32 on page 699
.
TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into internal shifter. Set to 0 when writing into TWI_THR.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the
same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode
can be seen in
Figure 34.7.3.4 on page 679
.
TXRDY used in Slave mode:
0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK).
1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged.
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the
programmer must not fill TWI_THR to avoid losing it.
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
TXBUFE
RXBUFF
ENDTX
ENDRX
EOSACC
SCLWS
ARBLST
NACK
7
–
6
5
4
3
2
1
0
OVRE
GACC
SVACC
SVREAD
TXRDY
RXRDY
TXCOMP