917
SAM4CP [DATASHEET]
43051E–ATPL–08/14
40.6.11.2 Oversampling Digital Output Range
When an oversampling is performed, the maximum value that can be read on ADC_CDRx or ADC_LCDR is not the full
scale value, even if the maximum voltage is supplied on the analog input. This is due to the digital averaging algorithm.
For example, when OSR = 1, four samples are accumulated and the result is then right-shifted by 1 (divided by 2).
The maximum output value carried on ADC_CDRx or ADC_LCDR depends on the OSR value configured in ADC_EMR.
40.6.12 Buffer Structure
The PDC read channel is triggered each time a new data is stored in ADC_LCDR. The same structure of data is
repeatedly stored in ADC_LCDR each time a trigger event occurs. Depending on user mode of operation (ADC_MR,
ADC_CHSR, ADC_SEQR1) the structure differs. Each data read to the PDC buffer, carried on a half-word (16-bit),
consists of last converted data right-aligned. When TAG is set in ADC_EMR, the four most significant bits carry the
channel number, thus simplifying post-processing in the PDC buffer or improved checking of the PDC buffer integrity.
40.7
Register Write Protection
To prevent any single software error from corrupting ADC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the
“ADC Write Protection Mode Register”
(ADC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the
“ADC Write Protection Status Register”
(ADC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the ADC_WPSR.
The following registers can be write-protected:
“ADC Mode Register” on page 920
“ADC Channel Sequence 1 Register” on page 922
“ADC Channel Enable Register” on page 923
“ADC Channel Disable Register” on page 924
“ADC Temperature Sensor Mode Register” on page 931
“ADC Temperature Compare Window Register” on page 932
“ADC Extended Mode Register” on page 934
“ADC Compare Window Register” on page 936
“ADC Analog Control Register” on page 938
Table 40-4.
Oversampling Digital Output Range Values
Resolution
Samples
Shift
Full Scale Value
Maximum Value
8-bit
1
0
255
255
10-bit
1
0
1023
1023
11-bit
4
1
2047
2046
12-bit
16
2
4095
4092