542
SAM4CP [DATASHEET]
43051E–ATPL–08/14
The MULx field is the PLLx multiplier factor. This parameter can be programmed between 0 and 250. If MULx is
set to 0, PLLx will be turned off, otherwise the PLLx output frequency is PLLx input frequency multiplied by (MULx
+ 1).
The PLLxCOUNT field specifies the number of slow clock cycles before the LOCKx bit is set in the PMC_SR after
CKGR_PLLxR has been written.
Once CKGR_PLLxR has been written, the user must wait for the LOCKx bit to be set in the PMC_SR. This can be
done either by polling LOCKx in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt
source (LOCKx) has been enabled in PMC_IER. All fields in CKGR_PLLxR can be programmed in a single write
operation. If at some stage one of the following parameters, MULx or DIVx is modified, the LOCKx bit goes low to
indicate that PLLx is not yet ready. When PLLx is locked, LOCKx is set again. The user must wait for the LOCKx
bit to be set before using the PLLx output clock.
Select the master clock and processor clock:
7.
The master clock and the processor clock are configurable via PMC_MCKR.
The CSS field is used to select the clock source of the master clock and processor clock dividers. By default, the
selected clock source is the main clock.
The PRES field is used to define the processor clock and master clock prescaler. The user can choose between
different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the
PRES value.
Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR. This
can be done either by polling MCKRDY in PMC_SR or by waiting for the interrupt line to be raised if the associated
interrupt source (MCKRDY) has been enabled in PMC_IER. PMC_MCKR must not be programmed in a single
write operation. The programming sequence for PMC_MCKR is as follows:
If a new value for CSS field corresponds to PLL clock,
Program the PRES field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
Program the CSS field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
If a new value for CSS field corresponds to main clock or slow clock,
Program the CSS field in PMC_MCKR.
Wait for the MCKRDY bit to be set in the PMC_SR.
Program the PRES field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
If at some stage, parameters CSS or PRES are modified, the MCKRDY bit goes low to indicate that the master
clock and the processor clock are not yet ready. The user must wait for MCKRDY bit to be set again before using
the master and processor clocks.
Note: If PLLx clock was selected as the master clock and the user decides to modify it by writing in CKGR_PLLxR, the
MCKRDY flag will go low while PLLx is unlocked. Once PLLx is locked again, LOCKx goes high and MCKRDY is
set. While PLLx is unlocked, the master clock selection is automatically changed to slow clock for PLLA and main
clock for PLLB. For further information, see
Section 30.16.2 ”Clock Switching Waveforms”
.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
The Master Clock is main clock divided by 2.