久久免费精品五月天婷婷狠狠,午夜激情经典国产福利,国产亚洲精品理论片

您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358702 > E5551A-DIT (TEMIC SEMICONDUCTORS) SPECIALTY TELECOM CIRCUIT, UUC7 PDF資料下載

型號：	E5551A-DIT
廠商：	TEMIC SEMICONDUCTORS
元件分類：	通信及網(wǎng)絡(luò)
英文描述：	SPECIALTY TELECOM CIRCUIT, UUC7
封裝：	DIE-7
文件頁數(shù)：	748/1069頁
文件大小：	14303K
代理商：	E5551A-DIT

SAM4CP [DATASHEET]

43051E–ATPL–08/14

Drift Compensation

Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift.

To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle

from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is

between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the

RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock

cycle. These intervals are considered to be drift and so corrective actions are automatically taken.

Figure 36-10. Bit Resynchronization

36.6.3.3 Asynchronous Receiver

If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line.

The oversampling is either 16 or 8 times the baud rate clock, depending on the OVER bit in the US_MR.

The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected and data,

parity and stop bits are successively sampled on the bit rate clock.

If the oversampling is 16, (OVER to 0), a start is detected at the eighth sample to 0. Data bits, parity bit and stop bit are

assumed to have a duration corresponding to 16 oversampling clock cycles. If the oversampling is 8 (OVER to 1), a start

bit is detected at the fourth sample to 0. Data bits, parity bit and stop bit are assumed to have a duration corresponding to

8 oversampling clock cycles.

The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e.,

respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no

effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization

between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts

looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one

Oversampling

Expected edge

相關(guān)PDF資料	PDF描述
E5551A-DOW	SPECIALTY TELECOM CIRCUIT, UUC7
E5551A-FP008	SPECIALTY TELECOM CIRCUIT, PDSO8
E5551A-FP008	SPECIALTY TELECOM CIRCUIT, PDSO8
E5551A-DOW	SPECIALTY TELECOM CIRCUIT, UUC7
E5551A-DIT	SPECIALTY TELECOM CIRCUIT, UUC7

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
E5551A-DOW	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-FP008	制造商:未知廠家制造商全稱:未知廠家功能描述:TRANSPONDER\|CMOS\|SOP\|8PIN\|PLASTIC
E5552	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E555423	制造商:Elo Touch Solutions Inc 功能描述:1729L, 17-INCH LCD, CARROLLTOUCH, USB CONTROLLER, GRAY - Bulk
E55556-000	功能描述:電線鑒定 HTCM-SCE-TP-1/2-4H-4 RoHS:否制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長度:1 in

發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

(若只采購一條型號，填寫一行即可)

*型號	*數(shù)量	廠商	批號	封裝