322
SAM4CP [DATASHEET]
43051E–ATPL–08/14
19.5.2 Reinforced Safety Watchdog Timer Mode Register
Name:
RSWDT_MR
Address:
0x400E1504
Access:
Read/Write Once
Note:
Note:
The first write access prevents any further modification of the value of this register, read accesses remain possible.
The WDD and WDV values must not be modified within three slow clock periods following a restart of the watchdog
performed by means of a write access in the RSWDT_CR, else the watchdog may trigger an end of period earlier
than expected.
WDV: Watchdog Counter Value
Defines the value loaded in the 12-bit watchdog counter.
WDFIEN: Watchdog Fault Interrupt Enable
0: A Watchdog fault (underflow or error) has no effect on interrupt.
1: A Watchdog fault (underflow or error) asserts interrupt.
WDRSTEN: Watchdog Reset Enable
0: A Watchdog fault (underflow or error) has no effect on the resets.
1: A Watchdog fault (underflow or error) triggers a watchdog reset.
WDRPROC: Watchdog Reset Processor
0: If WDRSTEN is 1, a watchdog fault (underflow or error) activates all resets.
1: If WDRSTEN is 1, a watchdog fault (underflow or error) activates the processor reset.
WDD: Watchdog Delta Value
Defines the permitted range for reloading the watchdog timer.
If the watchdog timer value is less than or equal to WDD, writing RSWDT_CR with WDRSTT = 1 restarts the timer.
If the watchdog timer value is greater than WDD, writing RSWDT_CR with WDRSTT = 1 causes a Watchdog error.
WDDBGHLT: Watchdog Debug Halt
0: The watchdog runs when the processor is in debug state.
1: The watchdog stops when the processor is in debug state.
WDIDLEHLT: Watchdog Idle Halt
0: The watchdog runs when the system is in idle mode.
1: The watchdog stops when the system is in idle state.
31
–
30
–
29
28
27
26
25
24
WDIDLEHLT
WDDBGHLT
WDD
23
22
21
20
19
18
17
16
WDD
15
14
13
12
11
10
9
8
WDDIS
WDRPROC
WDRSTEN
WDFIEN
WDV
7
6
5
4
3
2
1
0
WDV