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SAM4CP [DATASHEET]
43051E–ATPL–08/14
26.7
Arbitration
The Bus Matrix provides an arbitration mechanism that reduces latency when conflict occurs, i.e. when two or more
masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrating each
slave specifically.
The Bus Matrix provides the user with the possibility of choosing between two arbitration types or mixing them for each
slave:
1.
Round-robin arbitration (default)
2.
Fixed priority arbitration
The resulting algorithm may be complemented by selecting a default master configuration for each slave.
When re-arbitration must be done, specific conditions apply. See
Section 26.7.1 “Arbitration Scheduling” on page 407
.
26.7.1 Arbitration Scheduling
Each arbiter has the ability to arbitrate between two or more master requests. In order to avoid burst breaking and also to
provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles:
1.
Idle cycles: When a slave is not connected to any master or is connected to a master which is not currently
accessing it.
2.
Single cycles: When a slave is currently doing a single access.
3.
End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For defined burst length, predicted
end of burst matches the size of the transfer but is managed differently for undefined burst length. See
“Undefined
Length Burst Arbitration” on page 407
.
4.
Slot cycle limit: When the slot cycle counter has reached the limit value, indicating that the current master access
is too long and must be broken. See
“Slot Cycle Limit Arbitration” on page 408
.
26.7.1.1 Undefined Length Burst Arbitration
In order to prevent long AHB burst lengths that can lock the access to the slave for an excessive period of time, the user
can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be selected from the
following Undefined Length Burst Type (ULBT) possibilities:
1.
Unlimited: no predetermined end of burst is generated. This value enables 1-Kbyte burst lengths.
2.
1-beat bursts: predetermined end of burst is generated at each single transfer during the INCR transfer.
3.
4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR transfer.
4.
8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR transfer.
5.
16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR
transfer.
6.
32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during INCR
transfer.
7.
64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during INCR
transfer.
8.
128-beat bursts: predetermined end of burst is generated at the end of each 128-beat boundary during INCR
transfer.
The use of undefined length 8-beat bursts or less is discouraged since this may decrease the overall bus bandwidth due
to arbitration and slave latencies at each first access of a burst.
However, if the usual length of undefined length bursts is known for a master, it is recommended to configure the ULBT
according to this length.
This selection can be done through the ULBT field of the Master Configuration Registers (MATRIX_MCFG).