875
SAM4CP [DATASHEET]
43051E–ATPL–08/14
39.5.2 Power Management
The SLCD Controller is clocked by the slow clock (SLCK). All the timings are based upon a typical value of 32 kHz for
SLCK.
The LCD segment/common pad buffers are supplied by the VDDLCD domain.
39.5.3 Interrupt Sources
The SLCD Controller interrupt line is connected to one of the internal sources of the Interrupt Controller. Using the SLCD
Controller interrupt requires prior programming of the Interrupt Controller.
39.5.4 Number of Segments and Commons
The product, embeds 46 segments and 5 Commons.
39.6
Functional Description
The use of the SLCDC comprises three phases of functionality: initialization sequence, display phase and disable
sequence.
1.
Initialization Sequence:
Select the LCD supply source in the shutdown controller.
Internal: the On-chip LCD Power Supply is selected.
External: the external supply source has to be between 2.5 to 3.6V.
Select the clock division (SLCDC_FRR) to use a proper frame rate.
Enter the number of common and segments terminals (SLCDC_MR).
Select the bias in compliance with the LCD manufacturer data sheet (SLCDC_MR).
Enter buffer driving time (SLCDC_MR).
Define the segments remapping pattern if required (SLCDC_SMR0/1).
2.
3.
4.
5.
6.
1.
During the Display Phase:
Data may be written at any time in the SLCDC memory, they are automatically latched and displayed at the next
LCD frame.
It is possible to:
Adjust contrast.
Adjust the frame frequency.
Adjust buffer driving time.
Reduce the SLCDC consumption by entering in low-power waveform at any time.
Use the large set of display features such as blinking, inverted blink, etc.
2.
Disable Sequence:
There are two ways to disable the SLCDC.
1.
By using the SLCDC_CR [LCDDIS] bit (recommended method).In this case, SLCDC configuration and memory
content are maintained.
2.
By using the SWRST (Software Reset) bit that acts like a hardware reset for SLCDC only.
Table 39-4.
Peripheral IDs
Instance
ID
SLCDC
32