160
SAM4CP [DATASHEET]
43051E–ATPL–08/14
E
If present, any
NaN
operand causes an
Invalid Operation
exception.
Otherwise, only a signaling
NaN
causes the exception.
Sd
is the floating-point operand to compare.
Sm
is the floating-point operand that is compared with.
Operation
This instruction:
1.
Compares:
Two floating-point registers.
One floating-point register and zero.
Writes the result to the FPSCR flags.
Restrictions
2.
This instruction can optionally raise an
Invalid Operation
exception if either operand is any type of NaN. It always raises an
Invalid Operation exception if either operand is a signaling NaN.
Condition Flags
When this instruction writes the result to the FPSCR flags, the values are normally transferred to the ARM flags by a sub-
sequent VMRS instruction.
Examples
VCMP.F32 S4, #0.0
VCMP.F32 S4, S2
12.6.11.4 VCVT, VCVTR between Floating-point and Integer
Converts a value in a register from floating-point to a 32-bit integer.
Syntax
VCVT{
R
}{
cond
}.
Tm
.F32
Sd
,
Sm
VCVT{
cond
}.F32.
Tm
Sd
,
Sm
where:
R
If
R
is specified, the operation uses the rounding mode specified by the FPSCR. If
R
is omitted.
the operation uses the Round towards Zero rounding mode.
cond
is an optional condition code, see
“Conditional Execution”
.
Tm
is the data type for the operand. It must be one of:
S32 signed 32-
U32 unsigned 32-bit value.
Sd, Sm
are the destination register and the operand register.
Operation
These instructions:
1.
Either
Converts a value in a register from floating-point value to a 32-bit integer.
Converts from a 32-bit integer to floating-point value.
Places the result in a second register.
The floating-point to integer operation normally uses the
Round towards Zero
rounding mode, but can optionally use the
rounding mode specified by the FPSCR.
2.
The integer to floating-point operation uses the rounding mode specified by the FPSCR.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.