176
SAM4CP [DATASHEET]
43051E–ATPL–08/14
12.6.12.4 DSB
Data Synchronization Barrier.
Syntax
DSB{
cond
}
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do
not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses
before it complete.
Condition Flags
This instruction does not change the flags.
Examples
DSB ; Data Synchronisation Barrier
12.6.12.5 ISB
Instruction Synchronization Barrier.
Syntax
ISB{
cond
}
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following
the ISB are fetched from memory again, after the ISB instruction has been completed.
Condition Flags
This instruction does not change the flags.
Examples
ISB ; Instruction Synchronisation Barrier
12.6.12.6 MRS
Move the contents of a special register to a general-purpose register.
Syntax
MRS{
cond
}
Rd
,
spec_reg
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Rd
is the destination register.
spec_reg
can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI,
BASEPRI_MAX, FAULTMASK, or CONTROL.
Operation
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the
Q flag.
In process swap code, the programmers model state of the process being swapped out must be saved, including
relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use
MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence.
Note:
See
“MSR”
.
BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.