787
SAM4CP [DATASHEET]
43051E–ATPL–08/14
36.7.12 USART Channel Status Register (SPI_MODE)
Name:
US_CSR (SPI_MODE)
Address:
0x40024014 (0), 0x40028014 (1), 0x4002C014 (2), 0x40030014 (3), 0x40034014 (4)
Access:
Read-only
This configuration is relevant only if USART_MODE = 0xE or 0xF in the
“USART Mode Register” on page 774
.
RXRDY: Receiver Ready (automatically set / reset)
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being
received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
TXRDY: Transmitter Ready (automatically set / reset)
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as
the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
TXEMPTY: Transmitter Empty (automatically set / reset)
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
UNRE: Underrun Error
0: No SPI underrun error has occurred since the last RSTSTA.
1: At least one SPI underrun error has occurred since the last RSTSTA.
ENDRX: End of Receive Buffer Interrupt Enable
ENDTX: End of Transmit Buffer Interrupt Enable
TXBUFE: Transmit Buffer Empty Interrupt Enable
RXBUFF: Receive Buffer Full Interrupt Enable
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
11
10
9
8
–
RXBUFF
TXBUFE
UNRE
TXEMPTY
7
–
6
–
5
4
3
2
–
1
0
OVRE
ENDTX
ENDRX
TXRDY
RXRDY