268
SAM4CP [DATASHEET]
43051E–ATPL–08/14
15.4
Functional Description
15.4.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and generates
the following reset signals:
proc_nreset: Processor reset line. It also resets the Watchdog Timer
coproc_nreset: Coprocessor (second processor) reset line
periph_nreset: Affects the whole set of embedded peripherals
coproc_periph_nreset: Affects the whole set of embedded peripherals driven by the Co- processor
nrst_out: Drives the NRST pin
These reset signals are asserted by the Reset Controller, either on events generated by peripherals, events on NRST
pin, or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the
NRST Manager when an assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.
The Reset Controller Mode Register (RSTC_MR), used to configure the Reset Controller, is powered with VDDBU, so
that its configuration is saved as long as VDDBU is on.
15.4.2 NRST Manager
After power-up, NRST is an output during the External Reset Length (ERSTL) time period defined in the RSTC_MR.
When the ERSTL time has elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND
by an external signal.
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager.
Figure 15-2
shows the block diagram of the NRST Manager.
Figure 15-2.
NRST Manager
15.4.2.1 NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported
to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing a 0
to the URSTEN in the RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in the Reset Controller Status Register
(RSTC_SR). As soon as the NRST pin is asserted, the URSTS in RSTC_SR is set. This bit clears only when RSTC_SR
is read.
The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, set the
URSTIEN bit in the RSTC_MR.
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
rstc_irq
Other
interrupt
sources
user_reset