SAM4CP [DATASHEET]
43051E–ATPL–08/14
6
2.
Block Diagram
Figure 2-1.
SAM4CP16B 176-pin Block Diagram
High Speed AHB Multilayer Bus Matrix 0
SAM4CP
ARST
Digital
Voltage
Regulator
PDC0
PDC0
TC[3..5]
TIOA[3:5]
TIOB[3:5]
TCLK[3:5]
USART0
UART0
TWCK0
TWD0
TWD1
URXD0
UTXD0
TXD0
SCK0
TWCK1
TIOB[0:2]
TCLK[0:2]
TIOA[0:2]
TWI0
TWI1
PDC0
PDC0
PDC0
PDC0
PDC0
ROM
(SAM-BA
CPKCL)
FLASH
1024 kB
SRAM 0
128 kB
USART1
TXD1
SCK1
USART2
TXD2
SCK2
USART3
RXD3
SCK3
RTS3
USART4
TXD4
SCK4
ADVREF
True Random
Number Generator
AES
PDC0
ICM (SHA)
(Integrity
Checker Module)
DMA
CPKCC
(Classical Public
Key Cryptography
Controller)
AD[0:1]
AD[3..5]
ADTRG
10-bit ADC
AHB to APB
Bridge 0
SRAM 2
8 kB
TD
TDOTTKSWCK
TM/WDO
JAGE
SRAM 1
16 kB
P
COM[0..4]
SEG[3..47]
SEG49
Segment LCD
Controller
Asynchronous
ABridge
UART1
URXD1
UTXD1
PDC1
PDC1
SPI1
SPI1_NPCS0
SPCK1
PWM[0:3]
PWM
Interprocessor
Communication
(IPC1)
Inter-processor
Communication
(IPC0)
High Speed AHB Multilayer Bus Matrix 1
Serial Wire and JTAG Debug Port (SW-DP / SWJ-DP)
N
V
I
C
Cortex-M4F
CM4P1
DSP
FPU
AHB-AP
System bus
N
V
I
C
DSP
AHB-AP
MPU
ICode / DCode bus
ICode / DCode bus
System bus
Cortex-M4
CM4P0
Timer Counter A
TC[0..2]
Timer Counter B
AHB to APB
Bridge 1
Instr./Data
Cache
Controller
2 kB Cache
Memory
I/D Bus
S Bus
S Bus
Master
Master
Master
Master
Master/Slave
Master/Slave
Master
Master
Slave/Master
Slave/Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Instr./Data
Cache
Controller
2 kB Cache
Memory
Peripheral
DMA 1
Peripheral
DMA 0
Master
Real Time Timer
XTAL OSC
32 kHz
Supply
Controller
Backup Zone
Reset
Controller
Backup Reg (16)
POR
RC 32 kHz
Supp.Mon
PMC
PIO Controller
8 MHz
PLLB
High Freq
.
RC OSC
4/8/12 MHz
XTAL OSC
3 - 20 MHz
System Controller
TST
PCK
[0:2]
XIN
XOUT
Automatic
Power Switch
Core Voltage
Regulator
LCD Voltage
Regulator
VDDBU
VDDIO
NRST
FWUP
XIN32
ERASE
XOUT32
VDDCORE
VDDPLL
VDDIN
VDDOUT
VDDLCD
TMP
[1:3]
TMP0
RTCOUT0
SHDN
PPLC
VRC
VIPA
PLL INIT
P
r
o
x
y
P
L
C
C
o
n
t
r
o
l
l
e
r
PDC0
Analog
Voltage
Regulator
VDDIN AN
VDDOUT AN
VDDIN PLC
VDDOUT PLC
PLL
VDDPLL PLC
SPI1_NPCS[1:3]
Real Time Clock
Time Stamping
Anti-tampering
Dual Watchdog
Sub-system 0
Sub-system 1
ECC
Temp. Sensor
PDC0
Digital Averager
Optical Port