參數(shù)資料
型號(hào)： Embedded Pentium 200
廠商： Intel Corp.
英文描述： 32 Bit Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術(shù)奔騰處理器)
中文描述： 32位嵌入式MMX技術(shù)（32位嵌入式帶MMX公司的技術(shù)奔騰處理器Pentium處理器）
文件頁(yè)數(shù)： 20/46頁(yè)
文件大?。?/td> 944K
代理商： EMBEDDED PENTIUM 200
Pentium
Processor with MMX Technology
20
Datasheet
HOLD
I
In response to the
bus hold request
, the processor floats most of its output and
input/output pins and asserts HLDA after completing all outstanding bus cycles.
The processor maintains its bus in this state until HOLD is deasserted. HOLD is
not recognized during LOCK cycles. The processor recognizes HOLD during
reset.
IERR#
O
The
internal error
pin is used to indicate internal parity errors. When a parity
error occurs on a read from an internal array, the processor asserts the IERR#
pin for one clock and then shuts down.
IGNNE#
I
This is the
ignore numeric error
input. This pin has no effect when the NE bit in
CR0 is set to 1. When the CR0.NE bit is 0, and the IGNNE# pin is asserted, the
processor ignores any pending unmasked numeric exception and continues
executing floating-point instructions for the entire duration that this pin is
asserted. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending
unmasked numeric exception exists (SW.ES = 1), and the floating-point
instruction is one of FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI,
FDISI, or FSETPM, the processor executes the instruction in spite of the pending
exception. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending
unmasked numeric exception exists (SW.ES = 1), and the floating-point
instruction is one other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW,
FENI, FDISI, or FSETPM, the processor stops execution and waits for an
external interrupt.
IGNNE# is internally masked when the processor is configured as a Dual
processor.
INIT
I
The processor
initialization
input pin forces the processor to begin execution in
a known state. The processor state after INIT is the same as the state after
RESET except that the internal caches, write buffers, and floating-point registers
retain the values they had prior to INIT. INIT may not be used instead of RESET
after power-up.
When INIT is sampled high when RESET transitions from high to low, the
processor performs a built-in self test prior to the start of program execution.
INTR/LINT0
I
An active
maskable interrupt
input indicates that an external interrupt has been
generated. When the IF bit in the EFLAGS register is set, the processor
generates two locked interrupt acknowledge bus cycles and vectors to an
interrupt handler after the current instruction execution is completed. INTR must
remain active until the first interrupt acknowledge cycle is generated to ensure
that the interrupt is recognized.
When the local APIC is enabled, this pin becomes LINT0.
INV
I
The
invalidation
input determines the final cache line state (S or I) in case of an
inquire cycle hit. It is sampled together with the address for the inquire cycle in
the clock EADS# is sampled active.
KEN#
I
The
cache enable
pin is used to determine whether the current cycle is
cacheable or not and is consequently used to determine cycle length. When the
processor generates a cycle that can be cached (CACHE# asserted) and KEN#
is active, the cycle is transformed into a burst line fill cycle.
LINT0/INTR
I
When the APIC is enabled, this pin is
local interrupt 0
. When the APIC is
disabled, this pin is INTR.
LINT1/NMI
I
When the APIC is enabled, this pin is
local interrupt 1
. When the APIC is
disabled, this pin is NMI.
LOCK#
O
The
bus lock
pin indicates that the current bus cycle is locked. The Pentium
processor with MMX technology does not allow a bus hold when LOCK# is
asserted (but AHOLD and BOFF# are allowed). LOCK# goes active in the first
clock of the first locked bus cycle and goes inactive after the BRDY# is returned
for the last locked bus cycle. LOCK# is guaranteed to be deasserted for at least
one clock between back-to-back locked cycles.
Table 4. Quick Pin Reference (Sheet 4 of 7)
Symbol
Type
Name and Function
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