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參數(shù)資料
| 型號： | Embedded Pentium 200 |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術(shù)奔騰處理器) |
| 中文描述： | 32位嵌入式MMX技術(shù)（32位嵌入式帶MMX公司的技術(shù)奔騰處理器Pentium處理器） |
| 文件頁數(shù)： | 9/46頁 |
| 文件大小： | 944K |
| 代理商： | EMBEDDED PENTIUM 200 |
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Pentium
Processor with MMX Technology
Datasheet
9
The block diagram shows the two instruction pipelines, the “u” pipe and the “v” pipe. The u-pipe
can execute all integer and floating-point instructions. The v-pipe can execute simple integer
instructions and the FXCH floating-point instructions.
The separate code and data caches are shown in the block diagram. The data cache has two ports,
one for each of the two pipes (the tags are triple-ported to allow simultaneous inquire cycles). The
data cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to the
physical addresses used by the data cache.
The code cache, branch target buffer and prefetch buffers are responsible for getting raw
instructions into the execution units. Instructions are fetched from the code cache or from the
external bus. Branch addresses are remembered by the branch target buffer. The code cache TLB
translates linear addresses to physical addresses used by the code cache.
Figure 1. Pentium
Processor with MMX Technology Block Diagram
A6180-01
DP
Logic
Control
ROM
Control Unit
Address
Generate
(U Pipeline)
Address
Generate
(V Pipeline)
Control
Bus
Unit
64-Bit
Data
Bus
32-Bit
Address
Bus
Control
APIC
TLB
Data Cache
16 Kbytes
Data
Control
Branch
Target
Buffer
MMX
Unit
Prefetch
Address
Instruction
Pointer
Prefetch Buffers
Instruction Decode
Code Cache
16 Kbytes
TLB
128
64
32
32
32
32
32
32
80
80
Control
Register File
Add
Floating Point
Unit
64-Bit
Data Bus
32-Bit
Addr. Bus
32
Integer Register File
ALU
(U Pipline)
ALU
(V Pipline)
Barrel Shifter
Branch Verification
and Target Address
Divide
Multiply
Page
Unit
U-Pipeline
Connection
V-Pipeline
Connection
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