- 您現在的位置：買賣IC網 > PDF目錄362693 > Embedded Pentium 200 (Intel Corp.) 32 Bit Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術奔騰處理器) PDF資料下載
參數資料
| 型號： | Embedded Pentium 200 |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術奔騰處理器) |
| 中文描述： | 32位嵌入式MMX技術（32位嵌入式帶MMX公司的技術奔騰處理器Pentium處理器） |
| 文件頁數： | 21/46頁 |
| 文件大?。?/td> | 944K |
| 代理商： | EMBEDDED PENTIUM 200 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
Pentium
Processor with MMX Technology
Datasheet
21
M/IO#
O
The
memory/input-output
is one of the primary bus cycle definition pins. It is
driven valid in the same clock as the ADS# signal is asserted. M/IO#
distinguishes between memory and I/O cycles.
NA#
I
An active
next address
input indicates that the external memory system is ready
to accept a new bus cycle although all data transfers for the current cycle have
not yet completed. The processor issues ADS# for a pending cycle two clocks
after NA# is asserted. The processor supports up to two outstanding bus cycles.
NMI/LINT1
I
The
non-maskable interrupt
request signal indicates that an external non-
maskable interrupt has been generated.
When the local APIC is enabled, this pin becomes LINT1.
PBGNT#
I/O
Private bus grant
is the grant line that is used when two Pentium processors
with MMX technology are configured in dual processing mode, in order to
perform private bus arbitration. PBGNT# should be left unconnected if only one
Pentium processor with MMX technology exists in a system.
PBREQ#
I/O
Private bus request
is the request line that is used when two Pentium
processors with MMX technology are configured in dual processing mode, in
order to perform private bus arbitration. PBREQ# should be left unconnected
when only one processor exists in a system.
PCD
O
The
page cache disable
pin reflects the state of the PCD bit in CR3, the Page
Directory Entry, or the Page Table Entry. PCD provides an external cacheability
indication on a page by page basis.
PCHK#
O
The
parity check
output indicates the result of a parity check on a data read. It is
driven with parity status two clocks after BRDY# is returned. PCHK# remains low
one clock for each clock in which a parity error was detected. Parity is checked
only for the bytes on which valid data is returned.
When two Pentium processors with MMX technology are operating in dual
processing mode, PCHK# may be driven two or three clocks after BRDY# is
returned.
PEN#
I
The
parity enable
input (along with CR4.MCE) determines whether a machine
check exception will be taken as a result of a data parity error on a read cycle.
When this pin is sampled active in the clock a data parity error is detected, the
processor latches the address and control signals of the cycle with the parity
error in the machine check registers. When PEN# is sampled active and the
machine check enable bit in CR4 is set to “1”, the processor vectors to the
machine check exception before the beginning of the next instruction.
PHIT#
I/O
Private hit
is a hit indication used when two Pentium processors with MMX
technology are configured in dual processing mode, in order to maintain local
cache coherency. PHIT# should be left unconnected when only one processor
exists in a system.
PHITM#
I/O
Private modified hit
is a hit on a modified cache line indication used when two
Pentium processors with MMX technology are configured in dual processing
mode, in order to maintain local cache coherency. PHITM# should be left
unconnected if only one processor exists in a system.
PICCLK
I
The APIC interrupt controller serial data bus clock is driven into the
programmable interrupt controller clock
input of the processor.
This pin is 3.3-V-tolerant-only on the Pentium processor with MMX technology.
Please refer to the
Embedded Pentium
Processor Family Developer’s Manual
(order number 273204) for the CLK and PICCLK signal quality specification.
PICD0/[DPEN#]–
PICD1/[APICEN]
I/O
Programmable interrupt controller data lines 0
–
1
of the Pentium processor
with MMX technology comprise the data portion of the APIC 3-wire bus. They are
open-drain outputs that require external pull-up resistors. These signals are
multiplexed with DPEN# and APICEN respectively.
Table 4. Quick Pin Reference (Sheet 5 of 7)
Symbol
Type
Name and Function
相關PDF資料 |
PDF描述 |
|---|---|
| Embedded Pentium 266 | Low-Power Embedded Pentium Processor with MMX Technology(低能量嵌入式帶MMX技術奔騰處理器) |
| EMBMOD133 | Intel Embedded Processor Module(英特爾嵌入式微處理器模塊) |
| EMBMOD166 | Intel Embedded Processor Module() |
| EMC2DXV5T1 | Dual Common Base-Collector Bias Resistor Transistors |
| EMC2DXV5T5 | Dual Common Base-Collector Bias Resistor Transistors |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EMBER ZIGBEE DEV KIT W/PCWH | 制造商:Custom Computer Services (CCS) 功能描述:KIT DEV EMBER ZIGBEE W/PCWH |
| EMB-ET850-22 | 制造商:IBase Technology (USA) Inc. 功能描述:ET850 COM-E AMD N54L (2.2G) V/L - Bulk |
| EM-BFG11905-NJ | 功能描述:900MHZ FIBERGLASS BASESTATION AN 制造商:nearson inc. 系列:- 包裝:散裝 零件狀態(tài):在售 頻率組:UHF（300 MHz ~ 1 GHz） 頻率（中心/帶）:915MHz 頻率范圍:902MHz ~ 928MHz 天線類型:鞭狀，直形 頻帶數:1 VSWR:1.5 回波損耗:- 增益:5dBi 功率 - 最大值:100W 特性:- 端接:連接器，N 母型 侵入防護:IP66 安裝類型:連接器安裝 高度（最大值）:20.669"（525.00mm） 應用:- 標準包裝:1 |
| EMB-FTP-T-TM4C129-21P | 制造商:InterNiche Technologies 功能描述:EMBFTP (SERVER) - Virtual or Non-Physical Inventory (Software & Literature) |
| EMBFTP-T-TM4C129-21P | 制造商:InterNiche Technologies 功能描述:EMBTCP - Virtual or Non-Physical Inventory (Software & Literature) |
發(fā)布緊急采購，3分鐘左右您將得到回復。