參數(shù)資料
型號： Embedded Pentium 200
廠商： Intel Corp.
英文描述： 32 Bit Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術(shù)奔騰處理器)
中文描述： 32位嵌入式MMX技術(shù)（32位嵌入式帶MMX公司的技術(shù)奔騰處理器Pentium處理器）
文件頁數(shù)： 37/46頁
文件大?。?/td> 944K
代理商： EMBEDDED PENTIUM 200
Pentium
Processor with MMX Technology
Datasheet
37
3.4
AC Specifications
The AC specifications consist of output delays, input setup requirements and input hold
requirements. All AC specifications (with the exception of those for the TAP signals and APIC
signals) are relative to the rising edge of the CLK input.
All timings are referenced to 1.5 volts for both “0” and “1” logic levels unless otherwise specified.
Within the sampling window, a synchronous input must be stable for correct Pentium processor
with MMX technology operation.
Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer modeling
to account for signal flight time delays.
Each Pentium processor with MMX technology specified to operate within a single bus-to-core
ratio and a specific minimum to maximum bus frequency range (corresponding to a minimum to
maximum core frequency range). Operation in other bus-to-core ratios or outside the specified
operating frequency range is not supported. For example, the 166 MHz Pentium processor with
MMX technology does not operate beyond the 66 MHz bus frequency and only supports the 2/5
bus-to-core ratio; it does not support the 1/3, 1/2, or 2/3 bus-to-core ratios. Table 5 summarizes
these specifications.
Table 19. Input and Output Characteristics
Symbol
Parameter
Min
Max
Unit
Notes
C
IN
Input Capacitance
15
pF
Guaranteed by design
C
O
Output Capacitance
20
pF
Guaranteed by design
C
I/O
I/O Capacitance
25
pF
Guaranteed by design
C
CLK
CLK Input Capacitance
15
pF
Guaranteed by design
C
TIN
Test Input Capacitance
15
pF
Guaranteed by design
C
TOUT
Test Output Capacitance
20
pF
Guaranteed by design
C
TCK
Test Clock Capacitance
15
pF
Guaranteed by design
I
LI
Input Leakage Current
±15
μA
0 < V
< V
IL
,
V
IH
> V
IN
> V
CC
,
Note 1
I
LO
Output Leakage Current
±15
μA
0 < V
< V
,
V
IH
> V
IN
> V
CC
, Note 1
I
IH
Input Leakage Current
200
μA
V
IN
= 2.4 V, Note 2
I
IL
Input Leakage Current
–400
μA
V
IN
= 0.4 V, Notes 3, 4
NOTES:
1. This parameter is for inputs/outputs without an internal pull-up or pull-down.
2. This parameter is for inputs with an internal pull-down.
3. This parameter is for inputs with an internal pull-up.
4. This specification applies to the HITM# pin when it is driven as an input (e.g., in JTAG mode).
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