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參數(shù)資料
| 型號： | Embedded Pentium 200 |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術奔騰處理器) |
| 中文描述： | 32位嵌入式MMX技術（32位嵌入式帶MMX公司的技術奔騰處理器Pentium處理器） |
| 文件頁數(shù)： | 8/46頁 |
| 文件大?。?/td> | 944K |
| 代理商： | EMBEDDED PENTIUM 200 |
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Pentium
Processor with MMX Technology
8
Datasheet
1.1
Pentium
Processor Family Architecture
The application instruction set of the Pentium processor family includes the complete Intel486
processor family instruction set with extensions to accommodate some of the additional
functionality of the Pentium processor. All application software written for the Intel386 and
Intel486 family of microprocessors runs on Pentium processors without modification. The on-chip
memory management unit (MMU) is completely compatible with the Intel386 family and Intel486
family of processors.
Pentium processors implement several enhancements to increase performance. The two instruction
pipelines and the floating-point unit are capable of independent operation. Each pipeline issues
frequently used instructions in a single clock. Together, the dual pipes can issue two integer
instructions in one clock, or one floating-point instruction (under certain circumstances, two
floating-point instructions) in one clock.
Branch prediction is implemented in Pentium processors. To support this, the processor has two
prefetch buffers: one prefetches code in a linear fashion and the other prefetches code according to
the BTB so the needed code is almost always prefetched before it is needed for execution.
The floating-point unit (FPU) is up to ten times faster than the FPU used on the Intel486 processor
for common operations including add, multiply, and load.
Pentium processors include separate code and data caches that are integrated on-chip to meet
performance goals. Each cache has a 32-byte line size. Each cache has a dedicated Translation
Lookaside Buffer (TLB) to translate linear addresses to physical addresses. The data cache is
configurable to be write back or write through on a line-by-line basis and follows the MESI
protocol. The data cache tags are triple-ported to support two data transfers and an inquire cycle in
the same clock. The code cache is an inherently write-protected cache. The code cache tags are
multi-ported to support snooping. Individual pages can be configured as cacheable or non-
cacheable by software or hardware. The caches can be enabled or disabled by software or
hardware.
Pentium processors have a 64-bit data bus for fast data transfer. Burst read and burst writeback
cycles are supported. In addition, bus cycle pipelining allows two bus cycles to occur
simultaneously. The Memory Management Unit contains optional extensions to the architecture
which allow 4-Kbyte and 4-Mbyte page sizes.
Pentium processors have added significant data integrity and error detection capability. Data parity
checking is still supported on a byte-by-byte basis. Address parity checking and internal parity
checking features have been added along with a new exception, the machine check exception.
As more and more functions are integrated on chip, the complexity of board level testing is
increased. To address this, Pentium processors have increased test and debug capability. Pentium
processors implement IEEE Boundary Scan (Standard 1149.1). In addition, Pentium processors
provide four breakpoint pins that correspond to each of the debug registers and externally indicate a
breakpoint match. Execution tracing provides external indications when an instruction has
completed execution in either of the two internal pipelines, or when a branch has been taken.
System Management Mode (SMM) has been implemented along with some extensions to the SMM
architecture. Enhancements to the virtual 8086 mode have been made to increase performance by
reducing the number of times it is necessary to trap to a virtual 8086 monitor.
Figure 1 is a block diagram of the embedded Pentium processor with MMX technology.
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| EM-BFG11905-NJ | 功能描述:900MHZ FIBERGLASS BASESTATION AN 制造商:nearson inc. 系列:- 包裝:散裝 零件狀態(tài):在售 頻率組:UHF（300 MHz ~ 1 GHz） 頻率（中心/帶）:915MHz 頻率范圍:902MHz ~ 928MHz 天線類型:鞭狀，直形 頻帶數(shù):1 VSWR:1.5 回波損耗:- 增益:5dBi 功率 - 最大值:100W 特性:- 端接:連接器，N 母型 侵入防護:IP66 安裝類型:連接器安裝 高度（最大值）:20.669"（525.00mm） 應用:- 標準包裝:1 |
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