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參數(shù)資料
| 型號： | Embedded Pentium 233 |
| 廠商： | Intel Corp. |
| 英文描述： | 32 BIT Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術奔騰處理器) |
| 中文描述： | 32位嵌入式MMX技術（32位嵌入式帶MMX公司的技術奔騰處理器Pentium處理器） |
| 文件頁數(shù)： | 11/46頁 |
| 文件大?。?/td> | 944K |
| 代理商： | EMBEDDED PENTIUM 233 |
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Pentium
Processor with MMX Technology
Datasheet
11
1.2.1
Full Support for Intel’s MMX Technology
MMX technology is based on the Single Instruction Multiple Data (SIMD) technique which
enables increased performance on a wide variety of multimedia and communications applications.
Fifty-seven new instructions and four new 64-bit data types are supported in the embedded Pentium
processor with MMX technology. All existing operating system and application software are fully-
compatible with the embedded Pentium processor with MMX technology.
1.2.2
16-Kbyte Code and Data Cache
On-chip, level-one (L1) data and code cache sizes have been doubled to 16 Kbytes each. These
caches are 4-way set associative. Larger separate internal caches improve performance by reducing
average memory access time and providing fast access to recently-used instructions and data. The
instruction and data caches can be accessed simultaneously. The data cache supports two data
references simultaneously. The data cache supports a write back policy (or alternatively, write-
through, on a line-by-line basis) for memory updates. By default, the code cache is write-protected.
1.2.3
Improved Branch Prediction
Dynamic branch prediction uses the Branch Target Buffer (BTB) to boost performance by
predicting the most likely set of instructions to be executed. The BTB has been improved to
increase its accuracy. The embedded Pentium processor with MMX technology has four prefetch
buffers that can hold up to four successive code streams.
1.2.4
Enhanced Pipeline
An additional pipeline stage has been added and the pipeline has been enhanced to improve
performance. The integration of the MMX technology pipeline with the integer pipeline is very
similar to that of the floating-point pipeline. Under some circumstances, two MMX instructions or
one integer and one MMX instruction can be paired and issued in one clock cycle to increase
throughput.
The enhanced pipeline is described in more detail in the
Embedded Pentium
Processor Family
Developer’s Manual
(order number 273204).
1.2.5
Deeper Write Buffers
A pool of four write buffers is now shared between the dual pipelines to improve memory write
performance.
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