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參數(shù)資料
| 型號(hào)： | Embedded Pentium 233 |
| 廠商： | Intel Corp. |
| 英文描述： | 32 BIT Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術(shù)奔騰處理器) |
| 中文描述： | 32位嵌入式MMX技術(shù)（32位嵌入式帶MMX公司的技術(shù)奔騰處理器Pentium處理器） |
| 文件頁數(shù)： | 18/46頁 |
| 文件大?。?/td> | 944K |
| 代理商： | EMBEDDED PENTIUM 233 |
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Pentium
Processor with MMX Technology
18
Datasheet
BRDY#
I
The
burst ready
input indicates that the external system has presented valid
data on the data pins in response to a read or that the external system has
accepted the processor data in response to a write request. This signal is
sampled in the T2, T12 and T2P bus states.
BRDYC#
I
The
burst ready (copy)
is functionally identical to BRDY#.
BREQ
O
The
bus request
output indicates to the external system that the processor has
internally generated a bus request. This signal is always driven whether or not
the processor is driving its bus.
BUSCHK#
I
The
bus check
input allows the system to signal an unsuccessful completion of
a bus cycle. If this pin is sampled active, the processor latches the address and
control signals in the machine check registers. When the MCE bit in CR4 is set
and the BUSCHK# pin is active, the processor vectors to the machine check
exception.
To assure that BUSCHK# is always recognized, STPCLK# must be deasserted
any time BUSCHK# is asserted by the system, before the system allows another
external bus cycle. When BUSCHK# is asserted by the system for a snoop cycle
while STPCLK# remains asserted, usually (if MCE=1) the processor vectors to
the exception after STPCLK# is deasserted. But if another snoop to the same
line occurs during STPCLK# assertion, the processor can lose the BUSCHK#
request.
CACHE#
O
For processor-initiated cycles, the
cache
pin indicates internal cacheability of the
cycle (if a read), and indicates a burst write back cycle (when a write). When this
pin is driven inactive during a read cycle, the processor does not cache the
returned data, regardless of the state of the KEN# pin. This pin is also used to
determine the cycle length (number of transfers in the cycle).
CLK
I
The
clock
input provides the fundamental timing for the processor. Its frequency
is the operating frequency of the processor external bus, and requires TTL
levels. All external timing parameters except TDI, TDO, TMS, TRST#, and
PICD0–PICD1 are specified with respect to the rising edge of CLK.
This pin is 3.3-V-tolerant-only on the Pentium processor with MMX technology.
Please refer to the
Embedded Pentium
Processor Family Developer’s Manual
(order number 273204) for the CLK and PICCLK signal quality specification.
It is recommended that CLK begin toggling within 150 ms after V
reaches its
proper operating level. This recommendation is to ensure long-term reliability of
the device.
CPUTYP
I
CPU type
distinguishes the Primary processor from the Dual processor. In a
single processor environment, or when the processor is acting as the Primary
processor in a dual processing system, CPUTYP should be strapped to V
SS
. The
Dual processor should have CPUTYP strapped to V
CC3
.
D/C#
O
The
data/code
output is one of the primary bus cycle definition pins. It is driven
valid in the same clock as the ADS# signal is asserted. D/C# distinguishes
between data and code or special cycles.
D/P#
O
The
dual/primary
processor indication. The Primary processor drives this pin
low when it is driving the bus, otherwise it drives this pin high. D/P# is always
driven. D/P# can be sampled for the current cycle with ADS# (like a status pin).
This pin is defined only on the Primary processor. Dual processing is supported
in a system only if both processors are operating at identical core and bus
frequencies. Within these restrictions, two processors of different steppings may
operate together in a system.
D63–D0
I/O
These are the 64
data lines
for the processor. Lines D7–D0 define the least
significant byte of the data bus; lines D63–D56 define the most significant byte of
the data bus. When the processor is driving the data lines, they are driven during
the T2, T12, or T2P clocks for that cycle. During reads, the processor samples
the data bus when BRDY# is returned.
Table 4. Quick Pin Reference (Sheet 2 of 7)
Symbol
Type
Name and Function
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