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參數(shù)資料
| 型號： | Embedded Pentium 233 |
| 廠商： | Intel Corp. |
| 英文描述： | 32 BIT Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術(shù)奔騰處理器) |
| 中文描述： | 32位嵌入式MMX技術(shù)（32位嵌入式帶MMX公司的技術(shù)奔騰處理器Pentium處理器） |
| 文件頁數(shù)： | 23/46頁 |
| 文件大?。?/td> | 944K |
| 代理商： | EMBEDDED PENTIUM 233 |
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Pentium
Processor with MMX Technology
Datasheet
23
Core and bus frequencies can be set according to Table 5. Each Pentium processor with MMX
technology is specified to operate within a single bus-to-core ratio and a specific minimum-to-
maximum bus-frequency range (corresponding to a minimum-to-maximum core-frequency range).
Operation in other bus-to-core ratios or outside the specified operating frequency range is not
supported or advocated. For example, the 166 MHz Pentium processor with MMX technology does
not operate beyond the 66 MHz bus frequency and only supports the 2/5 bus-to-core ratio; it does
not support the 1/3, 1/2, or 2/3 bus-to-core ratios.
VSS
I
The Pentium processor with MMX technology has 53
ground
inputs.
W/R#
O
Write/read
is one of the primary bus cycle definition pins. It is driven valid in the
same clock as the ADS# signal is asserted. W/R# distinguishes between write
and read cycles.
WB/WT#
I
The
write back/write through
input allows a data cache line to be defined as
write back or write through on a line-by-line basis. As a result, it determines
whether a cache line is initially in the S or E state in the data cache.
Table 4. Quick Pin Reference (Sheet 7 of 7)
Symbol
Type
Name and Function
Table 5. Bus Frequency Selections
BF1
BF0
Bus/Core Ratio
Max Bus/Core
Frequency (MHz)
Min Bus/Core
Frequency (MHz)
0
1
1/3
66/200
33/100
0
0
2/5
N/A
(2)
N/A
(2)
1
0
1/2
(1,2)
N/A
(2)
N/A
(2)
1
1
2/7
66/233
33/117
NOTES:
1. This is the default bus to core ratio for the Pentium
processor with MMX technology. If the BF pins are
left floating, the processor will be configured for the 1/2 bus to core frequency ratio.
2. Currently, there are no embedded products that support these bus fractions.
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