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參數(shù)資料
| 型號： | Embedded Pentium 233 |
| 廠商： | Intel Corp. |
| 英文描述： | 32 BIT Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術奔騰處理器) |
| 中文描述： | 32位嵌入式MMX技術（32位嵌入式帶MMX公司的技術奔騰處理器Pentium處理器） |
| 文件頁數(shù)： | 19/46頁 |
| 文件大?。?/td> | 944K |
| 代理商： | EMBEDDED PENTIUM 233 |
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Pentium
Processor with MMX Technology
Datasheet
19
DP7–DP0
I/O
These are the
data parity
pins for the processor. There is one for each byte of
the data bus. They are driven by the processor with even parity information on
writes in the same clock as write data. Even parity information must be driven
back to the processor on these pins in the same clock as the data to ensure that
the correct parity check status is indicated by the processor. DP7 applies to
D63–D56, DP0 applies to D7–D0.
[DPEN#]
PICD0
I/O
Dual processing enable
is an output of the Dual processor and an input of the
Primary processor. The Dual processor drives DPEN# low to the Primary
processor at RESET to indicate that the Primary processor should enable dual
processor mode. DPEN# may be sampled by the system at the falling edge of
RESET to determine if the dual-processor socket is occupied. DPEN# is
multiplexed with PICD0.
EADS#
I
This signal indicates that a valid
external address
has been driven onto the
processor address pins to be used for an inquire cycle.
EWBE#
I
The
external write buffer empty
input, when inactive (high), indicates that a
write cycle is pending in the external system. When the processor generates a
write, and EWBE# is sampled inactive, the processor holds off all subsequent
writes to all E- or M-state lines in the data cache until all write cycles have
completed, which is indicated by EWBE# being active.
FERR#
O
The
floating-point error
pin is driven active when an unmasked
floating-point
error occurs. FERR# is similar to the ERROR# pin on the Intel387 math
coprocessor. FERR# is included for compatibility with systems using DOS-type
floating-point
error reporting. FERR# is never driven active by the Dual
processor.
FLUSH#
I
When asserted, the
cache flush
input forces the processor to write back all
modified lines in the data cache and invalidate its internal caches. A Flush
Acknowledge special cycle will be generated by the processor to indicate the
completion of the write back and invalidation.
When FLUSH# is sampled low when RESET transitions from high to low, three-
state test mode is entered.
When two Pentium processors with MMX technology are operating in dual
processing mode and FLUSH# is asserted, the Dual processor performs a flush
first (without a flush acknowledge cycle), then the Primary processor performs a
flush followed by a flush acknowledge cycle.
When the FLUSH# signal is asserted in dual processing mode, it must be
deasserted at least one clock prior to BRDY# of the FLUSH Acknowledge cycle
to avoid DP arbitration problems.
HIT#
O
The
hit
indication is driven to reflect the outcome of an inquire cycle. When an
inquire cycle hits a valid line in the processor data or instruction cache, this pin is
asserted two clocks after EADS# is sampled asserted. When the inquire cycle
misses the processor cache, this pin is negated two clocks after EADS#. This pin
changes its value only as a result of an inquire cycle and retains its value
between the cycles.
HITM#
O
The
hit to a modified line
output is driven to reflect the outcome of an inquire
cycle. It is asserted after inquire cycles which resulted in a hit to a modified line
in the data cache. It is used to inhibit another bus master from accessing the
data until the line is completely written back.
HLDA
O
The
bus hold acknowledge
pin goes active in response to a hold request driven
to the processor on the HOLD pin. It indicates that the processor has floated
most of the output pins and relinquished the bus to another local bus master.
When leaving bus hold, HLDA will be driven inactive and the Pentium processor
with MMX technology will resume driving the bus. If the processor has a bus
cycle pending, it will be driven one clock cycle after HLDA is deasserted.
Table 4. Quick Pin Reference (Sheet 3 of 7)
Symbol
Type
Name and Function
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