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參數(shù)資料
| 型號： | Embedded Pentium 233 |
| 廠商： | Intel Corp. |
| 英文描述： | 32 BIT Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術奔騰處理器) |
| 中文描述： | 32位嵌入式MMX技術（32位嵌入式帶MMX公司的技術奔騰處理器Pentium處理器） |
| 文件頁數(shù)： | 34/46頁 |
| 文件大?。?/td> | 944K |
| 代理商： | EMBEDDED PENTIUM 233 |
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Pentium
Processor with MMX Technology
34
Datasheet
These capacitors should be placed near the Pentium processor with MMX technology on both the
V
CC2
and V
CC3
plane to ensure that the supply voltage stays within specified limits during changes
in the supply current during operation.
Detailed decoupling recommendations are provided in
Flexible Motherboard Design Guidelines
(order number 243187).
Note:
Reducing available bulk capacitance could degrade long term system reliability.
3.1.3.4
3.3-V Inputs and Outputs
The inputs and outputs of the Pentium processor with MMX technology comply with the 3.3-V
JEDEC standard levels. Both inputs and outputs are also TTL-compatible, although the inputs
cannot tolerate voltage swings above the V
IN3
(max) specification.
System support components which use TTL-compatible inputs will interface to the Pentium
processor with MMX technology without extra logic. This is because the Pentium processor drives
according to the 5-V TTL specification (but not beyond 3.3 V).
For Pentium processor with MMX technology inputs, the voltage must not exceed the 3.3-V V
IN3
(max) specification. System support components can consist of 3.3-V devices or open-collector
devices. In an open-collector configuration, the external resistor should be biased to V
CC3
.
All pins, including the CLK and PICCLK of the Pentium processor with MMX technology, are
3.3 V-tolerant-only. When an 8259A interrupt controller is used, for example, the system must
provide level converters between the 8259A and the Pentium processor with MMX technology.
3.1.3.5
NC/INC and Unused Inputs
Important:
All NC and INC pins must remain unconnected.
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active
low inputs should be connected to V
CC3
. Unused active high inputs should be connected to V
SS
(ground).
3.1.3.6
Private Bus
When two Pentium processors with MMX technology are operating in dual processor mode, a
“private bus” exists to arbitrate for the processor bus and maintain local cache coherency. The
private bus consists of two pinout changes:
Five pins are added: PBREQ#, PBGNT#, PHIT#, PHITM#, D/P#.
Ten output pins become I/O pins: ADS#, D/C#, W/R#, M/IO#, CACHE#, LOCK#, HIT#,
HITM#, HLDA, SCYC, BE4#.
The new pins are given AC specifications of valid delays at 0 pF, setup times and hold times.
Simulate with these parameters and their respective I/O buffer models to guarantee that proper
timings are met.
The AC specification gives input setup and hold times for the ten signals that become I/O pins.
These setup and hold times must be met only when a dual processor is present in the system.
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