參數(shù)資料
型號(hào)： EPCS64SI16N
廠商： Altera
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 0K
描述： IC CONFIG DEVICE 64MBIT 16-SOIC
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 49
系列： EPCS
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 64Mb
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 管件
產(chǎn)品目錄頁(yè)面： 604 (CN2011-ZH PDF)
其它名稱： 544-1380-5
EPCS64SI16
EPCS64SI16N-ND
Page 20
EPCS Device Memory Access
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Write Status Operation
The write status operation code is b'0000 0001 and it lists the MSB first. Use the write
status operation to set the status register block protection bits. The write status
operation does not affect the other bits. Therefore, you can implement this operation
to protect certain memory sectors, as listed in Table 9 through Table 13. After setting
the block protect bits, the protected memory sectors are treated as read-only memory.
You must execute the write enable operation before the write status operation so the
device sets the status register’s write enable latch bit to 1.
The write status operation is implemented by driving the nCS signal low, followed by
shifting in the write status operation code and one data byte for the status register on
the ASDI pin. Figure 10 shows the instruction sequence of the write status operation.
The nCS must be driven high after the eighth bit of the data byte has been latched in,
otherwise the write status operation is not executed.
Immediately after the nCS signal drives high, the device initiates the self-timed write
status cycle. The self-timed write status cycle usually takes 5 ms for all EPCS devices
and is guaranteed to be less than 15 ms. For more information, refer to the tWS value in
Table 16 on page 29. You must account for this delay to ensure that the status register
is written with desired block protect bits. Alternatively, you can check the write in
progress bit in the status register by executing the read status operation while the
self-timed write status cycle is in progress. The write in progress bit is 1 during the
self-timed write status cycle and 0 when it is complete.
Read Bytes Operation
The read bytes operation code is b'0000 0011 and it lists the MSB first. To read the
memory contents of the EPCS device, the device is first selected by driving the nCS
signal low. Then, the read bytes operation code is shifted in followed by a 3-byte
address (A[23..0]). Each address bit must be latched in on the rising edge of the DCLK
signal. After the address is latched in, the memory contents of the specified address
are shifted out serially on the DATA pin, beginning with the MSB. For reading Raw
Programming Data files (.rpd), the content is shifted out serially beginning with the
LSB. Each data bit is shifted out on the falling edge of the DCLK signal. The maximum
DCLK
frequency during the read bytes operation is 20 MHz.
Figure 10. Write Status Operation Timing Diagram
nCS
DCLK
ASDI
DATA
0
1
2
3
4
5
6
7
8
9
101112131415
Operation Code
Status Register
76543210
MSB
High Impedance
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