參數(shù)資料
型號(hào)： EPCS64SI16N
廠商： Altera
文件頁數(shù)： 19/40頁
文件大?。?/td> 0K
描述： IC CONFIG DEVICE 64MBIT 16-SOIC
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 49
系列： EPCS
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 64Mb
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 管件
產(chǎn)品目錄頁面： 604 (CN2011-ZH PDF)
其它名稱： 544-1380-5
EPCS64SI16
EPCS64SI16N-ND
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2
6
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Figure 15 shows the instruction sequence of the write bytes operation.
Erase Bulk Operation
The erase bulk operation code is b'1100 0111 and it lists the MSB first. This operation sets all the memory bits to 1 or 0xFF.
Similar to the write bytes operation, you must execute the write enable operation before the erase bulk operation so that the
write enable latch bit in the status register is set to 1.
You can implement the erase bulk operation by driving the nCS signal low and then shifting in the erase bulk operation code on
the ASDI pin. The nCS signal must be driven high after the eighth bit of the erase bulk operation code has been latched in.
The device initiates a self-timed erase bulk cycle immediately after the nCS signal is driven high. For more information about
the self-timed erase bulk cycle time, refer to the tEB value in Table 16 on page 29.
You must account for this delay before accessing the memory contents. Alternatively, you can check the write in progress bit in
the status register by executing the read status operation while the self-timed erase cycle is in progress. The write in progress
bit is set to 1 during the self-timed erase cycle and 0 when it is complete. The write enable latch bit in the status register is reset
to 0 before the erase cycle is complete.
Figure 15. Write Bytes Operation Timing Diagram (1)
Notes to Figure 15:
(1) Use the erase sector operation or the erase bulk operation to initialize the memory bytes of the EPCS devices to all 1 or 0xFF before implementing the write bytes operation.
(2) Address bit A[23] is a don't-care bit in the EPCS64 device. Address bits A[23..21] are don't-care bits in the EPCS16 device. Address bits A[23..19] are don't-care bits in the EPCS4 device. Address
bits A[23..17] are don't-care bits in the EPCS1 device.
(3) For .rpd files, write the LSB of the data byte first.
nCS
DCLK
ASDI
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
2072 2073 2074 2075 2076 2077 2078 2079
Operation Code
24-Bit Address (2)
23
22
21
3
2
1
0
765
4
MSB
MSB (3)
Data Byte 1
Data Byte 2
Data Byte 256
321
0
765
4
7
65
4
321
0
321
0
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