參數(shù)資料
型號(hào): EPCS64SI16N
廠商: Altera
文件頁(yè)數(shù): 24/40頁(yè)
文件大?。?/td> 0K
描述: IC CONFIG DEVICE 64MBIT 16-SOIC
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 49
系列: EPCS
可編程類型: 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量: 64Mb
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
產(chǎn)品目錄頁(yè)面: 604 (CN2011-ZH PDF)
其它名稱: 544-1380-5
EPCS64SI16
EPCS64SI16N-ND
Page 30
Timing Information
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Figure 19 shows the timing waveform for the read operation of the EPCS device.
Table 17 lists the EPCS device timing parameters for the read operation.
1 Existing batches of EPCS1 and EPCS4 devices manufactured on 0.15 m process
geometry support the AS configuration up to 40 MHz. However, batches of EPCS1
and EPCS4 devices manufactured on 0.18 m process geometry support the AS
configuration only up to 20 MHz. EPCS16, EPCS64, and EPCS128 devices are not
affected.
f For more information about product traceability and transition date to differentiate
between 0.15 m process geometry and 0.18 m process geometry of the EPCS1 and
Figure 19. Read Operation Timing Diagram
nCS
DCLK
DATA
ASDI
tnCLK2D
tCL
tCH
tODIS
Bit N
Bit 0
Bit N
1
Add_Bit 0
Table 17. Read Operation Parameters
Symbol
Parameter
Min
Max
Unit
fRCLK
Read clock frequency (from the FPGA or
embedded processor) for the read bytes
operation
—20
MHz
Fast read clock frequency (from the FPGA or
embedded processor) for the fast read bytes
operation
—40
MHz
tCH
DCLK
high time
11
ns
tCL
DCLK
low time
11
ns
tODIS
Output disable time after read
8
ns
tnCLK2D
Clock falling edge to DATA
—8
ns
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