參數(shù)資料
型號(hào)： EPCS64SI16N
廠商： Altera
文件頁數(shù)： 15/40頁
文件大?。?/td> 0K
描述： IC CONFIG DEVICE 64MBIT 16-SOIC
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 49
系列： EPCS
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 64Mb
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 管件
產(chǎn)品目錄頁面： 604 (CN2011-ZH PDF)
其它名稱： 544-1380-5
EPCS64SI16
EPCS64SI16N-ND
Page 22
EPCS Device Memory Access
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Figure 11 shows the instruction sequence of the read bytes operation.
Fast Read Operation
The fast read operation code is b’0000 1011 and it lists the MSB first. You can select
the device by driving the nCS signal low. The fast read instruction code is followed by
a 3-byte address (A23-A0) and a dummy byte with each bit being latched-in during the
rising edge of the DCLK signal. Then, the memory contents at that address is shifted out
on DATA with each bit being shifted out at a maximum frequency of 40 MHz during
the falling edge of the DCLK signal.
The first addressed byte can be at any location. The address is automatically increased
to the next higher address after each byte of data is shifted out. Therefore, the whole
memory can be read with a single fast read instruction. When the highest address is
reached, the address counter rolls over to 000000h, allowing the read sequence to
continue indefinitely.
The fast read instruction is terminated by driving the nCS signal high at any time
during data output. Any fast read instruction is rejected during the erase, program, or
write operations without affecting the operation that is in progress.
Figure 11. Read Bytes Operation Timing Diagram
Notes to Figure 11:
(1) Address bit A[23] is a don't-care bit in the EPCS64 device. Address bits A[23..21] are don't-care bits in the EPCS16 device. Address bits
A[23..19]
are don't-care bits in the EPCS4 device. Address bits A[23..17] are don't-care bits in the EPCS1 device.
(2) For .rpd files, the read sequence shifts out the LSB of the data byte first.
nCS
DCLK
ASDI
DATA
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
Operation Code
24-Bit Address (1)
23
22
21
3
2
1
0
77
65
43
210
MSB
MSB (2)
High Impedance
DATA Out 1
DATA Out 2
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