參數(shù)資料
型號(hào)： EPCS64SI16N
廠商： Altera
文件頁數(shù)： 36/40頁
文件大?。?/td> 0K
描述： IC CONFIG DEVICE 64MBIT 16-SOIC
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 49
系列： EPCS
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 64Mb
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 管件
產(chǎn)品目錄頁面： 604 (CN2011-ZH PDF)
其它名稱： 544-1380-5
EPCS64SI16
EPCS64SI16N-ND
Active Serial FPGA Configuration
Page 5
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Figure 3 shows the configuration of an FPGA device in the AS configuration scheme
with an EPCS device using the APU or a third-party programmer.
In an AS configuration, the FPGA acts as the configuration master in the
configuration flow and provides the clock to the EPCS device. The FPGA enables the
EPCS device by pulling the nCS signal low using the nCSO signal as shown in Figure 2
and Figure 3. Then, the FPGA sends the instructions and addresses to the EPCS device
using the ASDO signal. The EPCS device responds to the instructions by sending the
configuration data to the FPGA’s DATA0 pin on the falling edge of DCLK. The data is
latched into the FPGA on the next DCLK signal’s falling edge.
1 Before the FPGA enters configuration mode, ensure that VCC of the EPCS device is
ready. If VCC is not ready, you must hold nCONFIG low until all power rails of EPCS
device are ready.
The FPGA controls the nSTATUS and CONF_DONE pins during configuration in the AS
mode. If the CONF_DONE signal does not go high at the end of configuration, or if the
signal goes high too early, the FPGA pulses its nSTATUS pin low to start a
reconfiguration. If the configuration is successful, the FPGA releases the CONF_DONE
pin, allowing the external 10-k resistor to pull the CONF_DONE signal high. The FPGA
initialization begins after the CONF_DONE pin goes high. After the initialization, the
FPGA enters user mode.
f For more information about configuring the FPGAs in AS configuration mode or
other configuration modes, refer to the configuration chapter in the appropriate
device handbook.
Figure 3. Altera FPGA Configuration in AS Mode Using APU or a Third-party Programmer (1), (4)
Notes to Figure 3:
(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.
(2) EPCS devices cannot be cascaded.
(3) Connect the MSEL[] input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration
chapter in the appropriate device handbook.
DATA
DCLK
nCS
ASDI
DATA0
DCLK
nCSO
nCE
nCONFIG
nSTATUS
MSEL[]
nCEO
CONF_DONE
ASDO
VCC (1) VCC (1) VCC (1)
10 k
Ω
10 k
Ω
10 k
Ω
(3)
Altera FPGA
EPCS Device (2)
N.C.
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