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參數(shù)資料
| 型號： | ET80960JT10016 |
| 廠商： | Intel |
| 文件頁數(shù)： | 11/86頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU I960JT 3V 100MHZ 132-QFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 處理器類型： | i960 |
| 特點(diǎn)： | 后綴 JT，32 位 16K 高速緩沖 |
| 速度： | 100MHz |
| 電壓： | 3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-QFP |
| 供應(yīng)商設(shè)備封裝： | 132-QFP |
| 包裝： | 托盤 |
| 其它名稱： | 864017 |
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80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Datasheet
19
BE[3:0]#
O
R(1)
H(Z)
P(1)
BYTE ENABLES select which of up to four data bytes on the bus participate in the
current bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
32-bit bus:
BE3# enables data on AD[31:24]
BE2# enables data on AD[23:16]
BE1# enables data on AD[15:8]
BE0# enables data on AD[7:0]
16-bit bus:
BE3# becomes Byte High Enable (enables data on AD[15:8])
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
BE0# becomes Byte Low Enable (enables data on AD[7:0])
8-bit bus:
BE3# is not used (state is high)
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
BE0# becomes Address Bit 0 (A0)
The processor asserts byte enables, byte high enable and byte low enable during Ta.
Since unaligned bus requests are split into separate bus transactions, these signals
do not toggle during a burst. They remain active through the last Td cycle.
For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A[3:2] described above.
WIDTH/
HLTD[1:0]
O
R(0)
H(Z)
P(1)
WIDTH/HALTED signals denote the physical memory attributes for a bus
transaction:
WIDTH/
HLTD1
WIDTH/
HLTD0
0
8 Bits Wide
0
1
16 Bits Wide
1
0
32 Bits Wide
1
Processor Halted
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in
response to a HOLD request, regardless of prior operating state.
D/C#
O
R(X)
H(Z)
P(Q)
DATA/CODE indicates that a bus access is a data access (1) or an instruction
access (0). D/C# has the same timing as W/R#.
0 = instruction access
1 = data access
W/R#
O
R(0)
H(Z)
P(Q)
WRITE/READ specifies, during a Ta cycle, whether the operation is a write (1) or
read (0). It is latched on-chip and remains valid during Td cycles.
0 = read
1 = write
DT/R#
O
R(0)
H(Z)
P(Q)
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
address/data bus. It is low during Ta and Tw/Td cycles for a read; it is high during Ta
and Tw/Td cycles for a write. DT/R# never changes state when DEN# is asserted.
0 = receive
1 = transmit
Table 8.
Pin Description—External Bus Signals (Sheet 2 of 4)
NAME
TYPE
DESCRIPTION
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