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參數(shù)資料
| 型號(hào)： | ET80960JT10016 |
| 廠商： | Intel |
| 文件頁數(shù)： | 2/86頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU I960JT 3V 100MHZ 132-QFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 處理器類型： | i960 |
| 特點(diǎn)： | 后綴 JT，32 位 16K 高速緩沖 |
| 速度： | 100MHz |
| 電壓： | 3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-QFP |
| 供應(yīng)商設(shè)備封裝： | 132-QFP |
| 包裝： | 托盤 |
| 其它名稱： | 864017 |
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80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
10
Datasheet
The Solutions960
program features a wide variety of development tools which support the i960
processor family. Many of these tools are developed by partner companies; some are developed by
Intel, such as profile-driven optimizing compilers. For more information on these products, contact
your local Intel representative.
2.1
80960 Processor Core
The 80960Jx family is a scalar implementation of the 80960 core architecture. Intel designed this
processor core as a very high performance device that is also cost-effective. Factors that contribute
to the core’s performance include:
Core operates at the bus speed with the 80960JA/JF/JS
Core operates at two or three times the bus speed with the 80960JD/JC and 80960JT,
respectively
Single-clock execution of most instructions
Independent Multiply/Divide Unit
Efficient instruction pipeline minimizes pipeline break latency
Register and resource scoreboarding allow overlapped instruction execution
128-bit register bus speeds local register caching
Two-way set associative, integrated instruction cache
Direct-mapped, integrated data cache
1-Kbyte integrated data RAM delivers zero wait state program data
Figure 2. 80960Jx Block Diagram
Programmable
Interrupt Controller
Control
Address/
Instruction Sequencer
Physical Region
Configuration
Interrupt
Port
1K Data RAM
Memory
Interface
Execution
Multiply
Unit
Divide
Unit
Memory-Mapped
Register Interface
Data Bus
Global / Local
Register File
SRC2
DEST
SRC1
address
Control
effective
Constants
Generation
Unit
Address
32-bit Address
32-bit Data
Bus Request
Queues
and
Two 32-Bit
Timers
8-Set
Local Register Cache
S
RC1
S
RC2
D
EST
PLL, Clocks,
Power Mgmt
Boundary Scan
Controller
TAP
5
CLKIN
SR
C
1
SR
C
2
DE
S
T
SR
C
1
D
EST
9
32
32-bit buses
address / data
21
Instruction Cache
80960JA - 2K
80960JF/JD - 4K
80960JS/JC/JT - 16K
Direct Mapped
Data Cache
80960JA - 1K
80960JF/JD - 2K
80960JS/JC/JT -
128
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
Bus
Control Unit
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