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參數(shù)資料
| 型號(hào)： | ET80960JT10016 |
| 廠商： | Intel |
| 文件頁(yè)數(shù)： | 14/86頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MPU I960JT 3V 100MHZ 132-QFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 處理器類型： | i960 |
| 特點(diǎn)： | 后綴 JT，32 位 16K 高速緩沖 |
| 速度： | 100MHz |
| 電壓： | 3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-QFP |
| 供應(yīng)商設(shè)備封裝： | 132-QFP |
| 包裝： | 托盤 |
| 其它名稱： | 864017 |
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80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Datasheet
21
HOLDA
O
R(Q)
H(1)
P(Q)
HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
relinquished control of the bus. The processor may grant HOLD requests and enter
the Th state during reset and while halted as well as during regular operation.
0 = hold not acknowledged
1 = hold acknowledged
BSTAT
O
R(0)
H(Q)
P(0)
BUS STATUS indicates that the processor may soon stall unless it has sufficient
access to the bus; see i960 Jx Microprocessor Developer’s Manual (272483).
Arbitration logic may examine this signal to determine when an external bus master
should acquire/relinquish the bus.
0 = no potential stall
1 = potential stall
Table 9.
Pin Description—Processor Control Signals, Test Signals, and Power (Sheet 1 of 2)
NAME
TYPE
DESCRIPTION
CLKIN
I
CLOCK INPUT provides the processor’s fundamental time base; both the processor
core and the external bus run at the CLKIN rate. All input and output timings are
specified relative to a rising CLKIN edge.
RESET#
I
A(L)
RESET initializes the processor and clears its internal logic. During reset, the
processor places the address/data bus and control output pins in their idle (inactive)
states.
During reset, the input pins are ignored with the exception of LOCK#/ONCE#,
STEST and HOLD.
The RESET# pin has an internal synchronizer. To ensure predictable processor
initialization during power up, RESET# must be asserted a minimum of 10,000
CLKIN cycles with VCC and CLKIN stable. On a warm reset, RESET# should be
asserted for a minimum of 15 cycles.
STEST
I
S(L)
SELF TEST enables or disables the processor’s internal self-test feature at
initialization. STEST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST is deasserted, the processor performs only the external bus confidence test.
0 = self test disabled
1 = self test enabled
FAIL#
O
R(0)
H(Q)
P(1)
FAIL indicates a failure of the processor’s built-in self-test performed during
initialization. FAIL# is asserted immediately upon reset and toggles during self-test to
indicate the status of individual tests:
When self-test passes, the processor deasserts FAIL# and begins operation
from user code.
When self-test fails, the processor asserts FAIL# and then stops executing.
0 = self test failed
1 = self test passed
TCK
I
TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
TDI
I
S(L)
TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising edge
of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
Table 8.
Pin Description—External Bus Signals (Sheet 4 of 4)
NAME
TYPE
DESCRIPTION
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