參數(shù)資料
型號: ET80960JT10016
廠商: Intel
文件頁數(shù): 66/86頁
文件大?。?/td> 0K
描述: IC MPU I960JT 3V 100MHZ 132-QFP
標(biāo)準(zhǔn)包裝: 1
處理器類型: i960
特點: 后綴 JT,32 位 16K 高速緩沖
速度: 100MHz
電壓: 3V
安裝類型: 表面貼裝
封裝/外殼: 132-QFP
供應(yīng)商設(shè)備封裝: 132-QFP
包裝: 托盤
其它名稱: 864017
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Datasheet
69
7.0
Bus Functional Waveforms
Figure 42 through Figure 47 illustrate typical 80960Jx bus transactions. Figure 48 depicts the bus
arbitration sequence. Figure 49 illustrates the processor reset sequence from the time power is
applied to the device. Figure 50 illustrates the processor reset sequence when the processor is in
operation. Figure 51 illustrates the processor ONCE# sequence from the time power is applied to
the device. Figure 53 and Figure 54 also show accesses on 32-bit buses. Table 44 through Table 46
summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to
data alignment.
Figure 42. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
CLKIN
AD31:0
ALE
ADS#
A3:2
BE3:0#
WIDTH1:0
D/C#
W/R#
DT/R#
DEN#
RDYRCV#
BLAST#
ADDR
D
In
Invalid
ADDR
DATA Out
10
Ta
Td
Tr
Ti
Ta
Td
Tr
Ti
F_JF030A
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