VDD,
參數(shù)資料
型號(hào): EVAL-AD9880-ABZ
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 23/64頁(yè)
文件大小: 0K
描述: KIT MODULE VIDEO INPUT AD9880
標(biāo)準(zhǔn)包裝: 1
主要目的: 視頻,視頻處理
嵌入式:
已用 IC / 零件: AD9880
主要屬性: HDMI 接收器和模擬接口
次要屬性: 3 路 8 位 150MSPS ADC
已供物品:
AD9880
Rev. 0 | Page 3 of 64
SPECIFICATIONS
ANALOG INTERFACE ELECTRICAL CHARACTERISTICS
VDD, VD = 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.
Table 1.
AD9880KSTZ-100
AD9880KSTZ-150
Parameter
Temp
Test Level
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
8
Bits
DC ACCURACY
Differential Nonlinearity
25°C
I
–0.6
+1.6/–
1.0
±0.7
+1.8/–
1.0
LSB
Integral Nonlinearity
25°C
I
±1.0
±2.1
±1.1
±2.25
LSB
No Missing Codes
Full
Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum
Full
VI
0.5
V p–p
Maximum
Full
VI
1.0
V p–p
Gain Tempco
+25°C
V
100
220
ppm/°C
Input Bias Current
+25°C
V
0.2
1
μA
Input Full-Scale Matching
25C
Full
VI
1.25
1.50
5
7
1.25
1.50
5
7
%FS
Offset Adjustment Range
Full
V
50
%FS
SWITCHING PERFORMANCE1
Maximum Conversion Rate
Full
VI
100
150
MSPS
Minimum Conversion Rate
Full
VI
10
MSPS
Data to Clock Skew
Full
IV
0.5
+2.0
0.5
+2.0
ns
Serial Port Timing
tBUFF
Full
VI
4.7
μs
tSTAH
Full
VI
4.0
μs
tDHO
Full
VI
0
μs
tDAL
Full
VI
4.7
μs
tDAH
Full
VI
4.0
μs
tDSU
Full
VI
250
ns
tSTASU
Full
VI
4.7
μs
tSTOSU
Full
VI
4.0
μs
HSYNC Input Frequency
Full
VI
15
110
15
110
KHz
Maximum PLL Clock Rate
Full
VI
100
150
MHz
Minimum PLL Clock Rate
Full
IV
12
MHz
PLL Jitter
+25°C
IV
700
ps p-p
Sampling Phase Tempco
Full
IV
15
ps/°C
DIGITAL INPUTS: (5V tolerant)
Input Voltage, High (VIH)
Full
VI
2.6
V
Input Voltage, Low (VIL)
Full
VI
0.8
V
Input Current, High (IIH)
Full
V
-82
μA
Input Current, Low (IIL)
Full
V
82
μA
Input Capacitance
25°C
V
3
pF
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Full
VI
VDD 0.1
V
Output Voltage, Low (VOL)
Full
VI
0.4
V
Duty Cycle, DATACK
Full
V
45
50
55
45
50
55
%
Output Coding
Binary
POWER SUPPLY
VD Supply Voltage
Full
IV
3.15
3.3
3.47
3.15
3.3
3.47
V
DVDD Supply Voltage
Full
IV
1.7
1.8
1.9
1.7
1.8
1.9
V
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