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參數(shù)資料
| 型號： | EVAL-AD9880-ABZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT MODULE VIDEO INPUT AD9880 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9880 |
| 主要屬性： | HDMI 接收器和模擬接口 |
| 次要屬性： | 3 路 8 位 150MSPS ADC |
| 已供物品： | 板 |
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AD9880
Rev. 0 | Page 45 of 64
Table 48. Output Clock Select
Select
Result
00
× pixel clock
01
1× pixel clock
10
2× pixel clock
11
90° phase 1× pixel clock
0x25
5-4
Output Drive Strength
These two bits select the drive strength for all the
high-speed digital outputs (except VSOUT, A0 and
O/E field). Higher drive strength results in faster
rise/fall times and in general makes it easier to capture
data. Lower drive strength results in slower rise/fall
times and helps to reduce EMI and digitally generated power
supply noise. The power-up default setting is 11.
Table 49. Output Drive Strength
Output Drive
Result
00
Low output drive strength
01
Medium low output drive strength
10
Medium high output drive strength
11
High output drive strength
0x25
3-2
Output Mode
These bits choose between four options for the output
mode, one of which is exclusive to an HDMI input.
4:4:4 mode is standard RGB; 4:2:2 mode is YCrCb,
which reduces the number of active output pins from
24 to 16; 4:4:4 double data rate (DDR) output mode;
and the data is RGB mode, but changes on every clock
edge. The power-up default setting is 00.
Table 50. Output Mode
Output
Mode
Result
00
4:4:4 RGB mode
01
4:2:2 YCrCb mode + DDR 4:2:2 on blue (secondary)
10
DDR 4:4:4: DDR mode + DDR 4:2:2 on blue
(secondary)
11
12-bit 4:2:2 (HDMI option only)
The power-up default is 00.
0x25
1
Primary Output Enable
This bit places the primary output in active or high
impedance mode.
The primary output is designated when using either
4:2:2 or DDR 4:4:4. In these modes, the data on the
red and green output channels is the primary output,
while the output data on the blue channel (DDR
YCrCb) is the secondary output. The power-up
default setting is 1.
Table 51. Primary Output Enable
Select
Result
0
Primary output is in high impedance mode
1
Primary output is enabled
0x25
0
Secondary Output Enable
This bit places the secondary output in active or high
impedance mode.
The secondary output is designated when using either
4:2:2 or DDR 4:4:4. In these modes the data on the
blue output channel is the secondary output while the
output data on the red and green channels is the
primary output. Secondary output is always a DDR
YCrCb data mode. The power-up default setting is 0.
Table 52. Secondary Output Enable
Select
Result
0
Secondary output is in high impedance mode
1
Secondary output is enabled
0x26
7
Output Three-State
When enabled, this bit puts all outputs (except
SOGOUT) in a high impedance state. The power-up
default setting is 0.
Table 53. Output Three-State
Select
Result
0
Normal outputs
1
All outputs (except SOGOUT) in high impedance mode
0x26
6
SOG Three-State
When enabled, this bit allows the SOGOUT pin to be
placed in a high impedance state. The power-up
default setting is 0.
Table 54. SOGout Three-State
Select
Result
0
Normal SOG output
1
SOGOUT pin is in high impedance mode
0x26
5
SPDIF Three-State
When enabled, this bit places the SPDIF audio output
pins in a high impedance state. The power-up default
setting is 0.
Table 55. SOGOUT Three-State
Select
Result
0
Normal SPDIF output
1
SPDIF pins in high impedance mode
0x26
4
I2S Three-State
When enabled, this bit places the I2S output pins in a
high impedance state. The power-up default setting
is 0.
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