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| 型號： | EVAL-AD9880-ABZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT MODULE VIDEO INPUT AD9880 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9880 |
| 主要屬性： | HDMI 接收器和模擬接口 |
| 次要屬性： | 3 路 8 位 150MSPS ADC |
| 已供物品： | 板 |
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AD9880
Rev. 0 | Page 15 of 64
Power Management
The AD9880 uses the activity detect circuits, the active interface
bits in the serial bus, the active interface override bits, the
power-down bit, and the power-down pin to determine the
correct power state. There are four power states: full-power,
seek mode, auto power-down and power-down.
Table 7 summarizes how the AD9880 determines which power
mode to be in and which circuitry is powered on/off in each of
these modes. The power-down command has priority and then
the automatic circuitry. The power-down pin (Pin 81—polarity
set by Register 0x26[3]) can drive the chip into four power-
down options. Bits 2 and 1 of Register 0x26 control these four
options. Bit 0 controls whether the chip is powered down or the
outputs are placed in high impedance mode (with the exception
of SOG). Bits 7 to 4 of Register 0x26 control whether the
outputs, SOG, Sony Philips digital interface (SPDIF ) or I2S (IIS
or Inter IC sound bus) outputs are in high impedance mode or
not. See the 2-Wire Serial Control Register Detail section for
the details.
Table 7. Power-Down Mode Descriptions
Inputs
Mode
Power-Down1
Sync Detect2
Auto PD Enable3
Power-On or Comments
Full Power
1
X
Everything
Seek Mode
1
0
Everything
Seek Mode
1
0
1
Serial bus, sync activity detect, SOG, band gap
reference
Power-Down
0
X
Serial bus, sync activity detect, SOG, band gap
reference
1 Power-down is controlled via Bit 0 in Serial Bus Register 0x26.
2 Sync detect is determined by OR’ing Bits 7 to 2 in Serial Bus Register 0x15.
3 Auto power-down is controlled via Bit 7 in Serial Bus Register 0x27
Table 8. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Standard
Resolution
Refresh Rate
Horizontal Frequency
Pixel Rate
VCO Range1
Current
VGA
640 × 480
60 Hz
31.5 kHz
25.175 MHz
00
101
72 Hz
37.7 kHz
31.500 MHz
01
011
75 Hz
37.5 kHz
31.500 MHz
01
100
85 Hz
43.3 kHz
36.000 MHz
01
100
SVGA
800 × 600
56 Hz
35.1 kHz
36.000 MHz
01
100
60 Hz
37.9 kHz
40.000 MHz
01
101
72 Hz
48.1 kHz
50.000 MHz
01
110
75 Hz
46.9 kHz
49.500 MHz
01
110
85 Hz
53.7 kHz
56.250 MHz
01
110
XGA
1024 × 768
60 Hz
48.4 kHz
65.000 MHz
10
011
70 Hz
56.5 kHz
75.000 MHz
10
100
75 Hz
60.0 kHz
78.750 MHz
10
100
80 Hz
64.0 kHz
85.500 MHz
10
101
85 Hz
68.3 kHz
94.500 MHz
10
110
SXGA
1280 × 1024
60 Hz
64.0 kHz
108.000 MHz
10
110
1280 × 1024
75 Hz
80.0 kHz
135.000 MHz
11
110
TV
480i
60 Hz
15.75 kHz
13.51 MHz
00
010
480p
60 Hz
31.47 kHz
27 MHz
00
101
720p
60 Hz
45 kHz
74.25 MHz
10
100
1035i
60 Hz
33.75 kHz
74.25 MHz
10
100
1080i
60 Hz
33.75 kHz
74.25 MHz
10
100
1080p
60 Hz
67.5 KHz
148.5 MHz
11
110
1 These are preliminary recommendations for the analog PLL and are subject to change without notice.
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