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參數(shù)資料
型號: EVAL-AD9880-ABZ
廠商: Analog Devices Inc
文件頁數(shù): 45/64頁
文件大小: 0K
描述: KIT MODULE VIDEO INPUT AD9880
標(biāo)準(zhǔn)包裝: 1
主要目的: 視頻,視頻處理
嵌入式:
已用 IC / 零件: AD9880
主要屬性: HDMI 接收器和模擬接口
次要屬性: 3 路 8 位 150MSPS ADC
已供物品:
AD9880
Rev. 0 | Page 5 of 64
AD9880KSTZ-100
AD9880KSTZ-150
Parameter
Test
Level
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
POWER SUPPLY
VD Supply Voltage
IV
3.15
3.3
3.47
3.15
3.3
3.47
V
VDD Supply Voltage
IV
1.7
3.3
347
1.7
3.3
347
V
DVDD Supply Voltage
IV
1.7
1.8
1.9
1.7
1.8
1.9
V
PVDD Supply Voltage
IV
1.7
1.8
1.9
1.7
1.8
1.9
V
IVD Supply Current (Typical Pattern)1
V
80
100
80
110
mA
IVDD Supply Current (Typical Pattern)2
V
40
1003
55
175*
IDVDD Supply Current (Typical Pattern)1, 4
V
88
110
145
mA
IPVDD Supply Current (Typical Pattern)1
V
26
35
30
40
mA
Power-Down Supply Current (IPD)
VI
130
mA
AC SPECIFICATIONS
Intrapair (+ to ) Differential Input Skew
(TDPS)
IV
360
pS
Channel to Channel Differential Input
Skew (TCCS)
IV
6
Clock
Period
Low-to-High Transition Time for Data and
Controls (DLHT)
IV
Output drive = high;
CL = 10 pF
900
ps
IV
Output drive = low;
CL = 5 pF
1300
ps
Low-to-High Transition Time for
DATACK (DLHT)
IV
Output drive = high;
CL = 10 pF
650
ps
IV
Output drive = low;
CL = 5 pF
1200
ps
High-to-Low Transition Time for Data and
Controls (DHLT)
IV
Output drive = high;
CL = 10 pF
850
ps
IV
Output drive = low;
CL = 5 pF
1250
ps
High-to-Low Transition Time for
DATACK (DHLT)
IV
Output drive = high;
CL = 10 pF
800
ps
IV
Output drive = low;
CL = 5 pF
1200
ps
Clock to Data Skew5 (TSKEW)
IV
–0.5
2.0
–0.5
2.0
ns
Duty Cycle, DATACK5
IV
45
50
55
%
DATACK Frequency (FCIP)
VI
20
150
MHz
1 The typical pattern contains a gray scale area, output drive = high. Worst case pattern is alternating black and white pixels.
2 The typical pattern contains a gray scale area, output drive = high.
3 Specified current and power values with a worst case pattern (on/off).
4 DATACK load = 10 pF, data load = 5 pF.
5 Drive strength = high.
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