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參數(shù)資料
| 型號： | EVAL-ADF4150HVEB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR ADF4150HV |
| 標準包裝： | 1 |
| 類型： | 整數(shù) N 合成器（RF） |
| 頻率： | 3GHz |
| 適用于相關(guān)產(chǎn)品： | ADF4150HV |
| 已供物品： | 板 |
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ADF4150HV
Rev. 0 | Page 19 of 28
REGISTER 3
Control Bits
When Bits[C3:C1] are set to 011, Register 3 is programmed.
Figure 23 shows the input data format for programming this
register.
Boost Enable
Setting the DB18 bit to 1 enables the charge pump boost mode.
If boost mode is enabled, the narrow loop bandwidth is main-
tained for spur attenuation, but faster lock times are still possible.
Boost mode speeds up locking significantly for higher values of
PFD frequencies that normally have many cycle slips.
When boost mode is enabled, an extra charge pump current cell
is turned on. This cell outputs a constant current to the loop filter
or removes a constant current from the loop filter (depending on
whether the VCO tuning voltage needs to increase or decrease
to acquire the new frequency) until VTUNE approaches the lock
voltage. The boost current is then disabled and the charge pump
current setting reverts to the user programmed value.
Loop stability is maintained because the current is constant and
is not pulsed, so there is no need to switch a compensating loop
filter resistor in and out, as in standard fast lock modes. Note that
the PFD requires a 45% to 55% duty cycle for the boost mode to
operate correctly. This duty cycle can be guaranteed by setting
the RDIV2 bit (DB24) in Register 2.
Clock Divider Mode
Bits[DB16:DB15] must be set to 10 to activate phase resync
(see the Phase Resync section). Setting Bits[DB16:DB15] to
00 disables the clock divider (see Figure 23).
12-Bit Clock Divider Value
Bits[DB14:DB3] set the 12-bit clock divider value. This value
is the timeout counter for activation of phase resync. For more
information, see the Phase Resync section.
REGISTER 4
Control Bits
When Bits[C3:C1] are set to 100, Register 4 is programmed.
Figure 24 shows the input data format for programming this
register.
Feedback Select
The DB23 bit selects the feedback from the VCO output to the
N counter. When this bit is set to 1, the signal is taken directly
from the VCO. When this bit is set to 0, the signal is taken from
the output of the output dividers. The dividers enable coverage
of the wide frequency band (31.25 MHz to 3.0 GHz). When the
dividers are enabled and the feedback signal is taken from the
output, the RF output signals of two separately configured PLLs
are in phase. This is useful in some applications where the posi-
tive interference of signals is required to increase the power.
Divider Select
Bits[DB22:DB20] select the value of the output divider (see
Mute-Till-Lock Detect (MTLD)
When the DB10 bit is set to 1, the supply current to the RF output
stage is shut down until the part achieves lock, as measured by
the digital lock detect circuitry.
RF Output Enable
The DB5 bit enables or disables the primary RF output. If DB5
is set to 0, the primary RF output is disabled; if DB5 is set to 1,
the primary RF output is enabled.
Output Power
Bits[DB4:DB3] set the value of the primary RF output power
level (see Figure 24).
REGISTER 5
Control Bits
When Bits[C3:C1] are set to 101, Register 5 is programmed.
Figure 25 shows the input data format for programming this
register.
Antibacklash Pulse Width
Bits[DB31:DB30] set the PFD antibacklash pulse width.
The recommended value for all operating modes is 4.2 ns
(set Bits[DB31:DB30] to 00). Other antibacklash pulse width
settings are reserved and are not recommended.
Charge Cancellation
Setting the DB29 bit to 1 enables charge pump charge cancel-
lation. This has the effect of reducing PFD spurs in integer-N
mode. In fractional-N mode, this bit should be set to 0.
Lock Detect Pin Operation
Bits[DB23:DB22] set the operation of the lock detect (LD) pin
(see Figure 25).
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after the correct application of voltages to
the supply pins, the ADF4150HV registers should be started in
the following sequence:
1.
Register 5
2.
Register 4
3.
Register 3
4.
Register 2
5.
Register 1
6.
Register 0
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