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參數(shù)資料
| 型號： | EVAL-ADF4150HVEB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR ADF4150HV |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 整數(shù) N 合成器（RF） |
| 頻率： | 3GHz |
| 適用于相關(guān)產(chǎn)品： | ADF4150HV |
| 已供物品： | 板 |
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ADF4150HV
Rev. 0 | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
09
05
8-
0
03
24 GND
23 GND
22 DVDD
21 PDBRF
20 AVDD
19 RFOUT+
18 RFOUT–
17 GND
1
2
3
4
5
6
7
8
GND
CLK
DATA
LE
CE
VP
GND
9
10
11
12
13
14
15
16
CP
OU
T
CP
GN
D
AV
DD
GN
D
AV
DD
RF
IN
+
RF
IN
–
GN
D
32
31
30
29
28
27
26
25
GN
D
R
SET
GN
D
SD
GN
D
SD
V
DD
MU
X
O
U
T
LD
RE
F
IN
ADF4150HV
TOP VIEW
(Not to Scale)
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
THAT MUST BE CONNECTED TO GND.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 7, 8, 12, 16, 17,
23, 24, 30, 32
GND
Ground. All ground pins should be tied together.
2
CLK
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
3
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a
high impedance CMOS input.
4
LE
Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into the register
that is selected by the three control bits. This input is a high impedance CMOS input.
5
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state
mode. A logic high on this pin powers up the device.
6
VP
High Voltage Charge Pump Power Supply. Place decoupling capacitors to the ground plane as close to
this pin as possible. The decoupling capacitors should have the appropriate voltage rating (a value of
10 μF is recommended). Care should be taken to ensure that VP does not exceed the absolute maximum
ratings on power-up (see Table 3). A 10 Ω series resistor can help to significantly reduce voltage overshoot
with minimal IR drop.
9
CPOUT
High Voltage Charge Pump Output. When enabled, this output provides ±ICP to the external passive loop
filter. The output of the loop filter is connected to the voltage tuning port of the external VCO.
10
CPGND
High Voltage Charge Pump Ground. All ground pins should be tied together.
11, 13, 20
AVDD
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the ground
plane as close to this pin as possible. AVDD must have the same value as DVDD.
14
RFIN+
Positive RF Input. The output of the VCO or external prescaler should be ac-coupled to this pin.
15
RFIN
Complementary RF Input. If a single-ended input is required, this pin can be tied to ground via a 100 pF
capacitor.
18
RFOUT
Divided-Down Output of RFIN. This pin can be left unconnected if the divider functionality is not
required.
19
RFOUT+
Divided-Down Output of RFIN+. This pin can be left unconnected if the divider functionality is not
required.
21
PDBRF
RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
22
DVDD
Digital Power Supply. Place decoupling capacitors to the ground plane as close to this pin as possible.
DVDD must have the same value as AVDD.
25
REFIN
Reference Input. This CMOS input has a nominal threshold of AVDD/2 and a dc equivalent input resistance
of 100 kΩ. This input can be driven from a crystal oscillator, TCXO, or other reference.
26
LD
Lock Detect Output. A logic high output on this pin indicates PLL lock. A logic low output indicates loss
of PLL lock.
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