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參數(shù)資料
| 型號： | EVAL-ADF4150HVEB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ADF4150HV |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 整數(shù) N 合成器（RF） |
| 頻率： | 3GHz |
| 適用于相關(guān)產(chǎn)品： | ADF4150HV |
| 已供物品： | 板 |
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ADF4150HV
Rev. 0 | Page 21 of 28
SPURIOUS OPTIMIZATION AND BOOST MODE
Narrow loop bandwidths can filter unwanted spurious signals,
but these bandwidths usually have a long lock time. A wider
loop bandwidth achieves faster lock times, but may lead to
increased spurious signals inside the loop bandwidth.
The boost mode feature can achieve the same fast lock time
as the wider bandwidth, but with the advantage of a narrow
final loop bandwidth to keep spurs low (see the Boost Enable
section).
SPUR MECHANISMS
This section describes the three different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4150HV.
Fractional Spurs
The fractional interpolator in the ADF4150HV is a third-order
Σ-Δ modulator with a modulus (MOD) that is programmable to
any integer value from 2 to 4095. In low spur mode (dither on),
the minimum allowable value of MOD is 50. The Σ-Δ modulator
is clocked at the PFD reference rate (fPFD), which allows PLL out-
put frequencies to be synthesized at a channel step resolution
of fPFD/MOD.
In low noise mode (dither off), the quantization noise from the
Σ-Δ modulator appears as fractional spurs. The interval between
spurs is fPFD/L, where L is the repeat length of the code sequence
in the digital Σ-Δ modulator. For the third-order Σ-Δ modulator
used in the ADF4150HV, the repeat length depends on the value
of MOD, as listed in Table 8.
Table 8. Fractional Spurs with Dither Off (Low Noise Mode)
MOD Value (Dither Off)
Repeat
Length
Spur Interval
MOD is divisible by 2, but not by 3
2 × MOD
Channel step/2
MOD is divisible by 3, but not by 2
3 × MOD
Channel step/3
MOD is divisible by 6
6 × MOD
Channel step/6
MOD is not divisible by 2, 3, or 6
MOD
Channel step
In low spur mode (dither on), the repeat length is extended
to 221 cycles, regardless of the value of MOD, which makes the
quantization error spectrum look like broadband noise. This
may degrade the in-band phase noise at the PLL output by as
much as 10 dB. For lowest noise, dither off is a better choice,
particularly when the final loop bandwidth is low enough to
attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation is the inter-
actions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related (the
purpose of a fractional-N synthesizer), spur sidebands appear
on the VCO output spectrum at an offset frequency that corre-
sponds to the beat note, or difference frequency, between an
integer multiple of the reference and the VCO frequency. These
spurs are attenuated by the loop filter and are more noticeable
on channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth (thus the
name integer boundary spurs).
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism that
bypasses the loop may cause a problem. The PCB layout must
ensure adequate isolation between VCO traces and the input
reference to avoid a possible feedthrough path on the board.
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
With dither off, the fractional spur pattern due to the quantiza-
tion noise of the Σ-Δ modulator also depends on the particular
phase word with which the modulator is seeded.
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Thus, a
lookup table of phase values corresponding to each frequency
can be constructed for use when programming the ADF4150HV.
If a lookup table is not used, keep the phase word at a constant
value to ensure consistent spur levels on any particular frequency.
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| EVAL-ADF4151EB1Z | 制造商:Analog Devices 功能描述:EVAL PLL FREQ SYNTH ADF4151 制造商:Analog Devices 功能描述:ADF4151, PLL SYNTHESIZER, EVAL BOARD; Silicon Manufacturer:Analog Devices; Kit Application Type:Clock & Timing; Application Sub Type:PLL Frequency Synthesizer; Kit Contents:Software CD, EVAL-ADF4151EB1Z Board; Features:Fractional-N ;RoHS Compliant: Yes |
| EVAL-ADF4153EB1 | 制造商:Analog Devices 功能描述:Evaluation Board For ADF4153 制造商:Analog Devices 功能描述:IC EVALUATION ((NS)) |
| EVAL-ADF4153EBZ1 | 功能描述:BOARD EVAL FOR ADF4153 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADF4154EB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N Frequency Synthesizer |
| EVAL-ADF4154EBZ1 | 功能描述:BOARD EVALUATION FOR ADF4154EB1 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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