參數(shù)資料
型號(hào)： EVAL-ADF4150HVEB1Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/28頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR ADF4150HV
標(biāo)準(zhǔn)包裝： 1
類型： 整數(shù) N 合成器（RF）
頻率： 3GHz
適用于相關(guān)產(chǎn)品： ADF4150HV
已供物品： 板
ADF4150HV
Rev. 0 | Page 20 of 28
RF SYNTHESIZER—A WORKED EXAMPLE
The following equations are used to program the ADF4150HV
synthesizer:
RFOUT = [INT + (FRAC/MOD)] × (fPFD/RF Divider)
(3)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
RF Divider is the output divider that divides down the VCO
frequency.
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(4)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit (0 or 1).
R is the RF reference division factor (1 to 1023).
T is the reference divide-by-2 bit (0 or 1).
In this example, the user wants to program a 1.5 GHz RF
frequency output (RFOUT) with a 500 kHz channel resolution
(fRESOUT) required on the RF output. The reference frequency
input (REFIN) is 25 MHz. The VCO options available to the
user include the following:
1.5 GHz VCO in fundamental mode
3 GHz VCO with the RF divider set to 2
When enabling the RF divider, the user must decide whether to
close the PLL loop before the RF divider or after it. In this
example, the PLL loop is closed before the RF divider (see
fPFD
PFD
VCO
N
DIVIDER
÷2
RFOUT
09
05
8-
02
2
Figure 26. PLL Loop Closed Before Output Divider
To minimize VCO feedthrough, the 3 GHz VCO is selected. A
channel resolution (fRESOUT) of 500 kHz is required at the output
of the RF divider. Therefore, the channel resolution at the output
of the VCO (fRES) needs to be 2 × fRESOUT, that is, 1 MHz.
MOD = REFIN/fRES
MOD = 25 MHz/1 MHz = 25
From Equation 4,
fPFD = [25 MHz × (1 + 0)/1] = 25 MHz
(5)
1500.5 MHz = 25 MHz × [(INT + (FRAC/25))/2]
(6)
where:
INT = 120.
FRAC = 1.
RF Divider = 2.
The ADF4150HV evaluation software can be used to help
determine integer and fractional values for a given setup,
along with the actual register settings to be programmed.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The on-chip reference doubler allows the input reference signal
to be doubled. Doubling the reference signal doubles the PFD
comparison frequency, which improves the noise performance
of the system. Doubling the PFD frequency usually improves
noise performance by 3 dB. Note that the PFD cannot operate
above 32 MHz due to a limitation in the speed of the Σ-Δ circuit
of the N divider.
The reference divide-by-2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. This is necessary
for the correct operation of the charge pump boost mode. For
more information, see the Boost Enable section.
12-BIT PROGRAMMABLE MODULUS
The choice of modulus (MOD) depends on the reference signal
(REFIN) available and the channel resolution (fRES) required at the
RF output. For example, a GSM system with 13 MHz REFIN sets
the modulus to 65. This means that the RF output resolution
(fRES) is the 200 kHz (13 MHz/65) necessary for GSM. With
dither off, the fractional spur interval depends on the modulus
values chosen (see Table 8).
Unlike most other fractional-N PLLs, the ADF4150HV allows
the user to program the modulus over a 12-bit range. When
combined with the reference doubler and the 10-bit R counter,
the 12-bit modulus allows the user to set up the part in many
different configurations for the application.
For example, consider an application that requires a 1.75 GHz
RF frequency output with a 200 kHz channel step resolution.
The system has a 13 MHz reference signal.
One possible setup is to feed the 13 MHz reference signal
directly into the PFD and to program the modulus to divide
by 65. This setup results in the required 200 kHz resolution.
Another possible setup is to use the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz is then fed
into the PFD, and the modulus is programmed to divide by 130.
This setup also results in 200 kHz resolution but offers superior
phase noise performance over the first setup.
The programmable modulus is also very useful for multistandard
applications with different channel spacing requirements.
It is important that the PFD frequency remain constant (in this
example, 13 MHz). This allows the user to design one loop filter
for both setups without encountering stability issues. Note that
the ratio of the RF frequency to the PFD frequency principally
affects the loop filter design, not the actual channel spacing.
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參數(shù)描述
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EVAL-ADF4154EBZ1 功能描述:BOARD EVALUATION FOR ADF4154EB1 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
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